Method for fabricating a power semiconductor device having a floating island voltage sustaining layer

• US 6,465,304 B1
• Filed: 10/04/2001
• Issued: 10/15/2002
• Est. Priority Date: 10/04/2001
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Guillot, Jean-Michel
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US09/970,972
• Time in Patent Office: 376 Days
• Field of Search: 438/268, 438/296, 438/424, 438/433, 438/434
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. depositing a barrier material along the walls of said trench;

4. implanting a dopant of a second conductivity type through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of said trench;

5. diffusing said dopant to form a first doped layer in said epitaxial layer;

6. removing the barrier material from at least the bottom of the trench;

7. etching the trench through said first doped layer; and

8. depositing a filler material in said trench to substantially fill said trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.

2. The method of claim 1 further comprising the steps of:

etching the trench to a greater depth and repeating steps (B.3)-(B.6) to form a second doped layer vertically below said first doped layer; and

etching the trench through said second doped layer.

3. The method of claim 1 wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.

4. The method of claim 1 wherein said barrier material is an oxide material.

5. The method of claim 4 wherein said oxide material is silicon dioxide.

6. The method of claim 1 wherein said epitaxial layer has a given thickness and further comprising the steps of:

D. etching the trench by an additional amount substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than two and corresponds to a prescribed number of doped layers to be formed in the voltage sustaining region;

E. repeating steps (B.3)-(B.6) to form another doped layer vertically below said first doped layer; and

F. repeating steps D-E until the prescribed number of doped layers have been formed; and

G. etching the trench through the xth layer of said doped layers.

7. The method of claim 1 wherein said material filling the trench is a dielectric material.

8. The method of claim 7 wherein said dielectric material is silicon dioxide.

9. The method of claim 7 wherein said dielectric material is silicon nitride.

10. The method of claim 1 wherein said dopant is boron.

11. The method of claim 3 wherein said body regions include deep body regions.

12. The method of claim 1, wherein said trench is formed by providing a masking layer defining at least one trench, and etching the trench defined by the masking layer.

13. The method of claim 3, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

14. The method of claim 1 wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMO, and a trench DMOS MOSFET, an IGBT, and a bipolar transistor.

15. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. depositing a barrier material along the walls of said trench;

4. implanting a dopant of a second conductivity type through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of said trench;

5. diffusing said dopant to form a first doped layer in said epitaxial layer;

6. removing the barrier material from at least the bottom of the trench;

7. depositing a filler material in said trench to substantially fill said trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.

16. The method of claim 15 further comprising the step of etching the trench through said first doped layer.

17. The method of claim 16 further comprising the steps of:

etching the trench to a greater depth and repeating steps (B.3)-(B.6) to form a second doped layer vertically below said first doped layer; and

etching the trench through said second doped layer.

18. The method of claim 15 wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.

19. The method of claim 15 wherein said barrier material is an oxide material.

20. The method of claim 19 wherein said oxide material is silicon dioxide.

21. The method of claim 16 wherein said epitaxial layer has a given thickness and further comprising the steps of:

D. etching the trench by an additional amount substantially equal to 1/(x1) of said given thickness, where x is equal to or greater than two and corresponds to a prescribed number of doped layers to be formed in the voltage sustaining region;

E. repeating steps (B.3)-(B.6) to form another doped layer vertically below said first doped layer; and

F. repeating steps D-E until the prescribed number of doped layers have been formed; and

G. etching the trench through the xth layer of said doped layers.

22. The method of claim 15 wherein said material filling the trench is a dielectric material.

23. The method of claim 22 wherein said dielectric material is silicon dioxide.

24. The method of claim 22 wherein said dielectric material is silicon nitride.

25. The method of claim 15 wherein said dopant is boron.