Method and structure for forming an electrode on a light emitting device

• US 6,465,808 B2
• Filed: 01/11/2001
• Issued: 10/15/2002
• Est. Priority Date: 11/24/2000
• Status: Expired due to Term

• Current Assignee: Epistar Corporation (Ennostar, Inc.)
• Original Assignee: Highlink Technology Corp. (Ennostar, Inc.)
• Inventors: Lin, Ming-Der
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US09/757,478
• Publication Number:
  US 20020063256A1
• Time in Patent Office: 642 Days
• Field of Search: 257/79, 257/81, 257/99, 257/98, 295/90, 372/50, 313/504, 313/503, 437/23
• US Class Current: 257/81
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/387 with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer

Abstract

A method and structure for forming an electrode on a light emitting device. The present invention provides a transparent electrode or a reflective electrode formed on a p-type gallium nitride-based compound semiconductor. The electrode comprises a plurality of opaque ohmic contact dots formed on the p-type gallium nitride-based compound semiconductor and a transparent conductive layer (or a light reflective conductive layer) covering the p-type gallium nitride-based compound semiconductor. Utilizing the present invention, the electrode is suitable for any light emitting device, and the light efficiency of the light emitting device is higher than that of the conventional light emitting device. Furthermore, the process of forming the electrode is easier than that of the conventional process.

Claims

1. A structure for forming an electrode on a light emitting device, comprising:

a semiconductor layer of said light emitting light device having a first surface and a second surface;

a plurality of annealed ohmic contact dots located on said first surface; and

a conductive layer covering said annealed ohmic contact dots and said first surface.

2. The structure according to claim 1, wherein said semiconductor is a gallium nitride-based III-V compound semiconductor.

3. The structure according to claim 2, wherein said semiconductor layer is a p-type gallium nitride-based III-V compound semiconductor.

4. The structure according to claim 3, wherein said annealed ohmic contact dots are formed of a metallic material comprising a layer of nickel provided in direct contact with said first surface, and a layer of gold provided on said nickel layer.

5. The structure according to claim 3, wherein said annealed ohmic contact dots are selected from a gold, a nickel, a platina, a palladium, a tungsten, a tungsten silicide, a chromium, a tantalum, a ZnAu alloy, and a BeAu alloy.

6. The structure according to claim 1, wherein said conductive layer is a transparent conductive layer.

7. The structure according to claim 6, wherein said transparent conductive layer is selected from an indium tin oxidation (ITO) layer, a cadmium tin oxidation (CTO) layer, an indium zinc oxidation (IZO) layer, a nickel oxidation (NiO) layer and a zinc oxidation (ZnO) layer.

8. The structure according to claim 1, wherein said conductive layer is a light reflective conductive layer.

9. The structure according to claim 8, wherein said light reflective conductive layer is selected from an argentum, a chromium, an aluminum, a gold, and a copper.

10. The structure according to claim 1, wherein said semiconductor is a GaAs-based compound semiconductor.

11. The structure according to claim 1, wherein said semiconductor is an InP-based compound semiconductor.

12. The structure according to claim 1, wherein said semiconductor is a GaP-based compound semiconductor.

13. The structure according to claim 1, wherein said semiconductor is a SiC-based compound semiconductor.

14. The structure according to claim 1, wherein said semiconductor is a ZnSe-based compound semiconductor.

15. A method for forming an electrode on a light emitting device, comprising:

forming a plurality of contact dots on a surface of a semiconductor layer of said light emitting light device;

processing a annealing treatment; and

forming a conductive layer covering said contact dots and said surface.

16. The method according to claim 15, wherein said semiconductor is a gallium nitride-based III-V compound semiconductor.

17. The method according to claim 16, wherein said semiconductor layer is a p-type gallium nitride-based III-V compound semiconductor.

18. The method according to claim 15, wherein said contact dots are formed of a metallic material comprising a layer of nickel provided in direct contact with said first surface, and a layer of gold provided on said nickel layer.

19. The method according to claim 15, wherein said ohmic contact dots are selected from a gold, a nickel, a platina, a palladium, a tungsten, a tungsten silicide, a chromium, a tantalum, a ZnAu alloy, and a BeAu alloy.

20. The method according to claim 15, wherein said contact dots have been subjected to an annealing treatment at a temperature of 400 degree. C. or more.

21. The method according to claim 15, wherein said conductive layer is a transparent conductive layer.

22. The method according to claim 21, wherein said transparent conductive layer is selected from an indium tin oxidation (ITO) layer, a cadmium tin oxidation (CTO) layer, an indium zinc oxidation (IZO) layer, a nickel oxidation (NiO) layer and a zinc oxidation (ZnO) layer.

23. The method according to claim 15, wherein said conductive layer is a light reflective conductive layer.

24. The method according to claim 23, wherein said light reflective conductive layer is selected from an argentum, a chromium, an aluminum, a gold, and a copper.

25. The method according to claim 15, wherein said semiconductor is a GaAs-based compound semiconductor.

26. The method according to claim 15, wherein said semiconductor is an InP-based compound semiconductor.

27. The method according to claim 15, wherein said semiconductor is a GaP-based compound semiconductor.

28. The method according to claim 15, wherein said semiconductor is a SiC-based compound semiconductor.

29. The method according to claim 15, wherein said semiconductor is a ZnSe-based compound semiconductor.

30. A structure for forming an electrode on a light emitting device, comprising:

a semiconductor layer of said light emitting light device having a first surface and a second surface;

a plurality of annealed ohmic contact dots located on said first surface; and

a conductive layer covering said annealed ohmic contact dots and said first surface, wherein said semiconductor layer is a p-type gallium nitride-based III-V compound semiconductor, and said annealed ohmic contact dots have been subjected to an annealing treatment at a temperature of 400 degree. C. or more.

31. The structure according to claim 30, wherein said annealed ohmic contact dots are formed of a metallic material comprising a layer of nickel provided in direct contact with said first surface, and a layer of gold provided on said nickel layer.

32. The structure according to claim 30, wherein said annealed ohmic contact dots are selected from a gold, a nickel, a platina, a palladium, a tungsten, a tungsten silicide, a chromium, a tantalum, a ZnAu alloy, and a BeAu alloy.

33. The structure according to claim 30, wherein said conductive layer is a transparent conductive layer.

34. The structure according to claim 33, wherein said transparent conductive layer is selected from an indium tin oxidation (ITO) layer, a cadmium tin oxidation (CTO) layer, an indium zinc oxidation (IZO) layer, a nickel oxidation (NiO) layer and a zinc oxidation (ZnO) layer.

35. The structure according to claim 30, wherein said conductive layer is a light reflective conductive layer.

36. The structure according to claim 35, wherein said light reflective conductive layer is selected from an argentum, a chromium, an aluminum, a gold, and a copper.

37. The structure according to claim 30, wherein said semiconductor layer is a GaAs-based compound semiconductor.

38. The structure according to claim 30, wherein said semiconductor layer is an InP-based compound semiconductor.

39. The structure according to claim 30, wherein said semiconductor layer is a GaP-based compound semiconductor.

40. The structure according to claim 30, wherein said semiconductor layer is a SiC-based compound semiconductor.

41. The structure according to claim 30, wherein said semiconductor layer is a ZnSe-based compound semiconductor.