Semiconductor device

• US 6,465,814 B2
• Filed: 06/27/2001
• Issued: 10/15/2002
• Est. Priority Date: 06/29/2000
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ohno, Yasuo, Takahashi, Yuji, Miyamoto, Hironobu, Kasahara, Kensuke, Nakayama, Tatsuo, Ando, Yuji, Hayama, Nobuyuki, Kunihiro, Kazuaki, Kuzuhara, Masaaki, Matsunaga, Kouji
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US09/891,419
• Publication Number:
  US 20020017648A1
• Time in Patent Office: 475 Days
• Field of Search: 257/365, 257/192, 257/280, 257/281, 257/194, 257/27, 257/29, 257/20, 257/96, 257/101, 257/458
• US Class Current: 257/192
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A semiconductor device of the present invention comprises Al_0.3Ga_0.7N layer 4 and Al_0.1Ga_0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al_0.3Ga_0.7N layer 4 is formed is used as a low resistance area, while an area where Al_0.1Ga_0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Claims

1. A semiconductor device, comprising:

an active layer; and

an electron supply layer in which induced charge including piezo charge is produced, said active layer and said electron supply layer being stacked in this order and having an interface between them at which a two-dimensional electron gas is formed,

wherein said induced charge has a substantially nonuniform distribution within a horizontal plane perpendicular to a thickness direction of said active layer and said electron supply layer and a distribution of a two-dimensional electron concentrations is formed within said horizontal plane in accordance with said substantially nonuniform distribution of said induced charge.

2. The semiconductor device according to claim 1, further comprising:

a gate electrode;

a source electrode; and

a drain electrode,

wherein a first area having a relatively low two-dimensional electron concentration is formed under said gate electrode and a second area having a relatively high two-dimensional electron concentration is formed under at least one of said source electrode, said drain electrode, an area between said gate electrode and said drain electrode, and an area between said gate electrode and said source electrode.

3. The semiconductor device according to claim 2, wherein said first area having a relatively low two-dimensional electron concentration comprises a higher resistance element and said second area having a relatively high two-dimensional electron concentration comprises a lower resistance element.

19. The semiconductor device according to claim 2, further comprising a second gate electrode between said gate electrode and said drain electrode.

4. A semiconductor device, comprising:

an active layer, said active layer comprising In_x Ga<sub>1−

x</sub>N (1≧

X≧

0); and

an electron supply layer formed in contact with an upper portion of said active layer and having a substantially nonuniform tensile strain within a horizontal plane perpendicular to a thickness direction of said electron supply layers said electron supply layer including a plurality of AlGaN layers, each of said plurality of AlGaN layers having a different average Al content.

5. The semiconductor device according to claim 4, wherein an Al content of at least one of said plurality of AlGaN layers increases with distance from said active layer.

6. The semiconductor device according to claim 4, further comprising:

a gate electrode;

a source electrode; and

a drain electrode,

wherein said gate electrode contacts one of said plurality of AlGaN layers, and other layers of said plurality of AlGaN layers have a higher Al content than said one of said plurality of AlGaN layers and are disposed between said gate electrode and said drain electrode and between said gate electrode and said source electrode.

7. The semiconductor device according to claim 5, further comprising:

a gate electrode;

a source electrode; and

a drain electrode,

wherein said gate electrode contacts one of said plurality of AlGaN layers, and other layers of said plurality of AlGaN layers have a higher Al content than said one of said plurality of AlGaN layers and are disposed between said gate electrode and said drain electrode and between said gate electrode and said source electrode.

8. The semiconductor device according to claim 4, wherein an area where a layer of said plurality of AlGaN layers having a relatively low Al content forms a higher resistance element and an area where a layer of said plurality of AlGaN layers having a relatively high Al content forms a lower resistance element.

9. The semiconductor device according to claim 5, wherein an area where a layer of said plurality of AlGaN layers having a relatively low Al content forms a higher resistance element and an area where a layer of said plurality of AlGaN layers having a relatively high Al content forms a lower resistance element.

20. The semiconductor device according to claim 6, further comprising a second gate electrode between said gate electrode and said drain electrode.

21. The semiconductor device according to claim 7, further comprising a second gate electrode between said gate electrode and said drain electrode.

10. A semiconductor device, comprising:

an active layer;

an electron supply layer formed in contact with an upper portion of said active layer and having a substantially nonuniform tensile strain; and

a strain layer formed in contact with a part of an upper portion of said electron supply layer and having a corresponding substantially nonuniform tensile strain,

wherein said active layer comprises In_xGa<sub>1−

x</sub>N (1≧

X≧

0), said electron supply layer comprises Al_YGa<sub>1−

Y</sub>N (Y≧

0), and said strain layer comprises Al_ZGa<sub>1−

Z</sub>N (1≧

Z>

Y).

11. The semiconductor device according to claim 10, wherein an Al content in at least one of said electron supply layer and said strain layer increase with distance from said active layer.

12. The semiconductor device according to claim 10, further comprising:

a gate electrode;

a source electrode; and

a drain electrode, wherein said gate electrode contacts said electron supply layer, and said strain layer is disposed between said gate electrode and said drain electrode and between said gate electrode and said source electrode.

13. The semiconductor device according to claim 11, further comprising:

a gate electrode;

a source electrode; and

a drain electrode, wherein said gate electrode contacts said electron supply layer, and said strain layer is disposed between said gate electrode and said drain electrode and between said gate electrode and said source electrode.

14. The semiconductor device according to claim 10, wherein an area where said strain layer is disposed forms a lower resistance element and an area where said strain layer is not disposed forms a higher resistance element.

15. The semiconductor device according to claim 11, wherein an area where said strain layer is disposed forms a lower resistance element and an area where said strain layer is not disposed forms a higher resistance element.

22. The semiconductor device according to claim 12, further comprising a second gate electrode between said gate electrode and said drain electrode.

23. The semiconductor device according to claim 13, further comprising a second gate electrode between said gate electrode and said drain electrode.

16. A semiconductor device, comprising:

an active layer; and

an electron supply layer formed in contact with an upper portion of said active layer and having a tensile strain,

wherein an Al content in said electron supply layer increases with distance from said active layer, a first area having a relatively low Al content is formed at a lower surface of said electron supply layer, and a second area having a relatively high Al content is formed at an upper surface of said electron supply layer.

17. The semiconductor device according to claim 16, further comprising:

a gate electrode;

a source electrode; and

a drain electrode,

wherein said gate electrode contacts said first area, and said second area is formed under at least one of said source electrode, said drain electrode, an area between said gate electrode and said drain electrode, and an area between said gate electrode and said source electrode.

18. The semiconductor device according to claim 16, wherein said first area comprises a higher resistance element and said second area comprises a lower resistance element.

24. The semiconductor device according to claim 17, further comprising a second gate electrode between said gate electrode and said drain electrode.