MOS-transistor structure with a trench-gate-electrode and a limited specific turn-on resistance and method for producing an MOS-transistor structure

• US 6,465,843 B1
• Filed: 04/27/2001
• Issued: 10/15/2002
• Est. Priority Date: 03/24/1999
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz, Werner, Wolfgang
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/701,291
• Time in Patent Office: 536 Days
• Field of Search: 438/268, 438/184, 438/270, 438/299, 438/302, 438/639, 257/331, 257/330, 257/332, 257/493, 257/369, 257/565, 257/396, 257/74
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

MOS transistor structure having a trench gate electrode and a reduced on resistance, and methods for fabricating a MOS transistor structure

A MOS transistor structure having a trench gate electrode and a reduced on resistance is described, the integral of the doping concentration of the body region in the lateral direction between two adjacent drift regions being greater than or equal to the integral of the doping concentration in a drift region in the same lateral direction.

Furthermore, methods for fabricating a MOS transistor structure are disclosed, body regions and drift regions being produced by epitaxial growth and implantation, repeated epitaxial growth or by filling trenches with doped conduction material.

Claims

1. A MOS transistor structure, comprising:

a highly doped substrate layer of a first conduction type which defines a first surface;

a second surface;

a body region of a second conduction type that is opposite to the first conduction type, said body region extending from said second surface to the substrate layer to define a depth;

a source region of the first conduction type, said source region extending from said second surface into said body region;

a trench formed in said body region and having a bottom, said trench extending from said second surface and being lined with a gate oxide;

a gate electrode located in said trench and having a depth that is smaller than said depth of said body region; and

drift regions of the first conduction type, said drift regions adjoining said bottom of said trench and extending as far as said substrate layer;

an integral of a doping concentration of said body region in a lateral direction between two adjacent ones of said drift regions is not less than an integral of a doping concentration in one of said drift regions in the lateral direction.

2. The transistor structure according to claim 1, wherein the integral of the doping concentration of said body region in the lateral direction is less than a breakdown charge.

3. The transistor structure according to claim 2, wherein the integral of the doping concentration of the body region in the lateral direction is a maximum of 2×

10¹² cm<sup>−

2</sup>.

4. The transistor structure according to claim 1, comprising an epitaxial layer forming said body region.

5. The transistor structure according to claim 1, wherein the doping concentration of said body region has a gradient.

6. A method for fabricating a MOS transistor structure, which comprises:

providing a highly doped substrate layer of a first conduction type;

epitaxially growing a body layer of a second conduction type on the highly doped substrate layer;

forming a source region in the body layer;

patterning a trench in the body layer such that the trench adjoins the source region and has a bottom;

implanting doping material of the first conduction type through the bottom of the trench into the body layer to produce a drift region extending from the bottom of the trench as far as the highly doped substrate layer;

before or after performing the step of implanting the doping material, forming a gate oxide layer that lines the trench; and

filling the trench with a gate electrode.

7. The method according to claim 6, which comprises, during the step of epitaxially growing the body layer, varying the doping concentration of the body layer.

8. The method according to claim 6, wherein the step of implanting the doping material includes a plurality of implantation steps having respectively different implantation energies.

9. The method according to claim 6, wherein the step of patterning the trench is performed by patterning the trench through the source region.

10. A method for fabricating a MOS transistor structure, which comprises:

providing a highly doped substrate layer of a first conduction type;

growing a sequence of doped, epitaxial partial layers of a given conduction type on the highly doped substrate layer;

after each process of growing one of the partial layers, producing doped regions in the one of the partial layers such that the sequentially produced doped regions and the sequentially produced partial layers together define pillar-type structured body regions and pillar-type structured drift regions;

producing the doped regions to have a conduction type opposite that of the given conduction type of the partial layers;

forming source regions in the body regions;

patterning trenches in the drift regions and producing the trenches to adjoin at least one of the body regions and at least one of the source regions;

lining the trenches with a gate oxide layer; and

filling the trenches with a gate electrode.

11. The method according to claim 10, which comprises:

before growing the sequence of the doped, epitaxial partial layers, providing a further drift region on the highly doped substrate layer.

12. A method for fabricating a MOS transistor structure, which comprises:

providing a highly doped substrate layer of a first conduction type;

providing a body layer of a second conduction type on the highly doped substrate layer;

forming trenches in the body layer;

filling the trenches with doped semiconductor material of the first conduction type;

etching back the doped semiconductor material as far as the body layer so that drift regions of the first conduction type and body regions of the second conduction type define a surface;

forming source regions in the body regions;

patterning trenches into the drift regions such that each one of the trenches adjoins at least one of the body regions and one of the source regions;

lining the trenches with a gate oxide layer; and

filling the trenches with a gate electrode.

13. The method according to claim 12, which comprises, before, providing the body layer, providing a first drift region on the highly doped substrate layer.

14. The method according to claim 13, which comprises:

using a mask to perform the step of patterning the trenches into the drift regions; and

using the mask to pattern the trenches for the electrode.

15. The method according to claim 12, which comprises:

using a mask to perform the step of patterning the trenches into the drift regions; and

using the mask to pattern the trenches for the electrode.

16. The method according to claim 12, which comprises:

setting a doping concentration of the body regions and of the drift regions such that an integral of the doping concentration in one of the drift regions in the lateral direction between two adjacent ones of the body regions is not greater than an integral of the doping concentration of one of the body regions in the same lateral direction.

17. The method according to claim 12, which comprises:

setting a doping concentration of the body regions such that an integral of the doping concentration in one of the body regions in a lateral direction is less than a breakdown charge.

18. The method according to claim 17, which comprises:

setting the doping concentration of the body regions such that the integral of the doping concentration in the one of the body regions in the lateral direction is, a maximum of 2·

10¹² cm<sup>−

2</sup>.

19. The method according to claim 12, which comprises forming the body regions with a doping concentration having a gradient.