Power semiconductor device and method of manufacturing the same

• US 6,465,844 B2
• Filed: 07/16/2001
• Issued: 10/15/2002
• Est. Priority Date: 07/17/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Omura, Ichiro, Saito, Wataru
• Primary Examiner(s): Ngô , Ngân V.
• Application Number:
  US09/904,888
• Publication Number:
  US 20020005549A1
• Time in Patent Office: 456 Days
• Field of Search: 257/335, 257/336, 257/337, 257/339, 257/341, 257/342
• US Class Current: 257/336
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A power semiconductor device has a plurality of U-shaped buried layers buried in a drift layer and made of either an insulating material or a semiconductor having a wider bandgap than that of the semiconductor of the drift layer. The ratio of the product of the height H of the U-shaped buried layers and the arrangement pitch d to the spacing g between adjacent ones of the U-shaped buried layers is expressed as Hd/g≦13.2. With this configuration, a power semiconductor device having both a high breakdown voltage and a low on resistance can be realized.

Claims

1. A power semiconductor device comprising:

a first semiconductor layer of a first conductivity type having a first and a second main surface that oppose to each other;

a first main electrode electrically connected to the second main surface of the first semiconductor layer;

a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer;

a third semiconductor layer of the first conductivity type selectively formed on a surface of the second semiconductor layer;

a second main electrode electrically connected to the surface of the second semiconductor layer and a surface of the third semiconductor layer;

a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; and

buried layers whose cross section is shaped like a letter U and which are made of either an insulating layer or a semiconductor layer having a wider bandgap than that of the first semiconductor layer and are provided in the first semiconductor layer in such a manner that a set of at least two of the buried layers are arranged with a pitch of d and a spacing of g in a horizontal direction perpendicular to a vertical direction passing through the first main electrode and the second main electrode and at least one stage of the set of at least two buried layers is arranged in the vertical direction,

a ratio A of a product of a height H of the U-shaped buried layers and the arrangement pitch d to the spacing g between adjacent ones of the U-shaped buried layers being expressed as;

2. The power semiconductor device according to claim 1, wherein the ratio A is expressed as:

3. The power semiconductor device according to claim 1, further comprising a Schottky barrier diode provided on the first semiconductor layer and connected in parallel with a built-in diode formed between the second semiconductor layer and the first semiconductor layer.

4. A power semiconductor device comprising:

a first semiconductor layer of a first conductivity type having a first and a second main surface that face each other;

a first main electrode electrically connected to the second main surface of the first semiconductor layer;

a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer;

a third semiconductor layer of the first conductivity type selectively formed on a surface of the second semiconductor layer;

a second main electrode electrically connected to the surface of the second semiconductor layer and a surface of the third semiconductor layer;

a gate electrode formed via a gate insulating film above the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; and

buried layers whose cross section is shaped like a letter U and which are made of either an insulating layer or a semiconductor layer having a wider bandgap than that of the first semiconductor layer and are provided in the first semiconductor layer in such a manner that a set of at least two of the buried layers are arranged with a pitch of d and a spacing of g in a horizontal direction perpendicular to a vertical direction passing through the first main electrode and the second main electrode and at least one stage of the set of at least two buried layers is arranged in the vertical direction,

a ratio B of a sum of a width W and a height H of the U-shaped buried layers to the arrangement pitch d being expressed as;

5. The power semiconductor device according to claim 4, wherein the ratio B is expressed as:

6. The power semiconductor device according to claim 4, wherein the ratio A of the product of the height H of the U-shaped buried layers and the arrangement pitch d to the spacing g between adjacent ones of the U-shaped buried layers is expressed as:

7. The power semiconductor device according to claim 4, further comprising a Schottky barrier diode provided on the first semiconductor layer and connected in parallel with a built-in diode formed between the second semiconductor layer and the first semiconductor layer.