System for testing bumped semiconductor components with on-board multiplex circuit for expanding tester resources

• US 6,466,047 B1
• Filed: 12/04/2001
• Issued: 10/15/2002
• Est. Priority Date: 05/11/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Doherty, C. Patrick, deVarona, Jorge L.
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US09/999,502
• Time in Patent Office: 315 Days
• Field of Search: 324/765, 324/158.1, 324/754, 324/755, 324/757, 324/758
• US Class Current: 324/750.25
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each component, and permits defective components to be electrically disconnected.

Claims

1. A test system for testing semiconductor components having a plurality of bumped contacts comprising:

a tester configured to transmit test signals to the components and to analyze resultant signals;

an interconnect comprising a plurality of interconnect contacts in electrical communication with the tester and configured to electrically engage the bumped contacts; and

a multiplex circuit on the interconnect in electrical communication with the interconnect contacts, the circuit configured to fan out the test signals from the tester, and to control the interconnect contacts to selectively transmit the test signals to the bumped contacts or to selectively read the resultant signals.

2. The test system of claim 1 further comprising a wafer prober configured to support the interconnect and to align and move the components into contact with the interconnect.

3. The test system of claim 1 wherein the interconnect contacts comprise conductive pockets.

4. The test system of claim 1 wherein the interconnect contacts comprise projections or edges configured to penetrate the bumped contacts.

5. The test system of claim 1 wherein the interconnect comprises a semiconductor material and the multiplex circuit comprises active electrical switching devices in the material.

6. The test system of claim 1 wherein the multiplex circuit comprises a die flip chip mounted to the interconnect.

7. A test system for testing semiconductor components comprising integrated circuits and a plurality of bumped contacts in electrical communication with the integrated circuits, the system comprising:

a tester configured to transmit test signals to the integrated circuits;

an interconnect comprising a plurality of interconnect contacts in electrical communication with the tester configured to electrically engage the bumped contacts; and

a multiplex circuit on the interconnect in electrical communication with the interconnect contacts and configured to multiply the test signals;

the multiplex circuit comprising a plurality of active electrical switching devices, each of the devices in electrical communication with an interconnect contact and operable by control signals to selectively enable and disable the interconnect contact, to allow the test signals to be selectively transmitted to the integrated circuits.

8. The test system of claim 7 wherein the interconnect contacts comprise conductive pockets.

9. The test system of claim 7 wherein the components are contained on a substrate.

10. The test system of claim 7 wherein the interconnect contacts comprise conductive pockets having projections therein configured to penetrate the bumped contacts.

11. The test system of claim 7 wherein the interconnect contacts comprise projections or edges for penetrating the bumped contacts.

12. The test system of claim 7 wherein the components comprise semiconductor packages.

13. The test system of claim 7 wherein the interconnect comprises a semiconductor material and the multiplex circuit comprises a plurality of active electrical switching devices fabricated therein.

14. The test system of claim 7 wherein the multiplex circuit comprises a semiconductor die on the interconnect.

15. The test system of claim 7 wherein the multiplex circuit comprises a bumped semiconductor die flip chip mounted to the interconnect.

16. A test system for testing semiconductor components on a substrate having a plurality of bumped contacts comprising:

a tester configured to transmit test signals to the components and to analyze resultant test signals;

an interconnect comprising a plurality of interconnect contacts in electrical communication the tester configured to electrically engage the bumped contacts; and

a multiplex circuit on the interconnect in electrical communication with the interconnect contacts, the circuit configured to fan out the test signals from the tester to a selected group of components on the substrate and to read the resultant test signals from the selected group.

17. The test system of claim 16 wherein the components comprise semiconductor dice and the substrate comprises a semiconductor wafer.

18. The test system of claim 16 wherein the components comprise semiconductor packages and the substrate comprises a panel or a leadframe.

19. The test system of claim 16 wherein the interconnect contacts comprise conductive pockets configured to retain the bumped contacts.

20. The test system of claim 16 wherein the interconnect contacts comprise projections or edges configured to penetrate the bumped contacts.

21. A test system for testing semiconductor components on a substrate having a plurality of bumped contacts comprising:

a tester configured to transmit write test signals to the components and to receive read test signals from the components, the tester having a signal writing capability and a signal reading capability;

an interconnect comprising a plurality of interconnect contacts in electrical communication with the tester configured to electrically engage the bumped contacts; and

a multiplex circuit on the interconnect in electrical communication with and configured to control the interconnect contacts, the circuit configured to expand the signal writing capability by multiplexing the write test signals to a selected group of interconnect contacts, and to read the read test signals from the selected group up to the signal reading capability.

22. The test system of claim 21 wherein the bumped contacts comprise solder balls and the interconnect contacts comprise conductive pockets configured to retain the solder balls.

23. The test system of claim 21 wherein the components comprise semiconductor dice on a wafer.

24. The test system of claim 21 wherein the components comprise semiconductor packages on a panel or leadframe.

25. The test system of claim 21 wherein the interconnect comprises a semiconductor material and the multiplex circuit comprises devices in the material.

26. The test system of claim 21 wherein the multiplex circuit comprises a semiconductor die on the interconnect.