Reduced static phase error CMOS PLL charge pump

• US 6,466,078 B1
• Filed: 05/04/2001
• Issued: 10/15/2002
• Est. Priority Date: 05/04/2001
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Stiff, Jonathon C.
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US09/849,164
• Time in Patent Office: 529 Days
• Field of Search: 327/157, 327/148, 327/536, 331/17
• US Class Current: 327/536
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.

Claims

1. An apparatus comprising:

a pump up circuit configured to generate a pump up signal in response to a first source bias, said pump up circuit comprises a first capacitance coupled to said first source bias configured to compensate for a positive switching voltage;

a pump down circuit configured to generate a pump down signal in response to a second source bias, said pump down circuit comprises a second capacitance coupled to said second source bias configured to compensate for a negative switching voltage; and

an output circuit configured to generate an output signal in response to said pump up and pump down signals, wherein said pump up circuit is configured to precharge said first source bias and said pump down circuit is configured to precharge said second source bias signal.

2. The apparatus according to claim 1, wherein:

said first capacitance comprises a first capacitor coupled between said first source bias and said positive switching voltage; and

said second capacitance comprises a second capacitor coupled between said second source bias and said negative switching voltage.

3. The apparatus according to claim 2, wherein:

said first capacitance comprises a third capacitor coupled between said first source bias and a first reference voltage; and

said second capacitance comprises a fourth capacitor coupled between said second source bias and a second reference voltage.

4. The apparatus according to claim 1, wherein said first source bias comprises a PMOS source bias and said second source bias comprises a NMOS source bias.

5. The apparatus according to claim 1, wherein said output circuit is further configured to receive a first cascode bias and a second cascode bias.

6. The apparatus according to claim 5, wherein said first cascode bias comprises a PMOS cascode bias and said second cascode bias comprises an NMOS cascode bias.

7. The apparatus according to claim 1, wherein said apparatus comprises a reduced static phase error CMOS PLL charge pump.

8. A method for reducing static phase error, comprising the steps of:

(A) generating a pump up signal in response to a first source bias and compensating for a positive switching voltage with a first capacitance coupled to said first source bias;

(B) generating a pump down signal in response to a second source bias and compensating for a negative switching voltage with a second capacitance coupled to said second source bias;

(C) generating an output signal in response to said pump up and pump down signals; and

(D) precharging said first source bias and said second source bias signal.

9. A method for reducing static phase error, comprising the steps of:

(A) generating a pump up signal with a first delay element comprising a first and a second inverting buffer coupled in series;

(B) generating a pump down signal with a second delay element comprising a third and a fourth inverting buffer coupled in series;

(C) generating an output signal in response to said pump up and pump down signals; and

(D) deglitching said pump up signal and said pump down signal.

10. The method according to claim 9, wherein:

step (A) further comprises compensating for a positive switching voltage with a first capacitance coupled to a first source bias; and

step (B) further comprises compensating for a negative switching voltage with a second capacitance coupled to a second source bias.

11. An apparatus comprising:

a pump up circuit (a) comprising a first delay element comprising a first and a second inverting buffer coupled in series and (b) configured to generate a pump up signal;

a pump down circuit comprising (a) a second delay element comprising a third and a fourth inverting buffer coupled in series and (b) configured to generate a pump down signal; and

an output circuit configured to (a) receive said pump up and pump down signals and (b) generate an output signal, wherein said pump up circuit is configured to deglitch said pump up signal and said pump down circuit is configured to deglitch said pump down signal.

12. The apparatus according to claim 11, wherein:

said pump up circuit further comprises a first capacitance coupled to a first source bias and configured to compensate for a positive switching voltage; and

said pump down circuit further comprises a second capacitance coupled to a second source bias and configured to compensate for a negative switching voltage.

13. The apparatus according to claim 11, wherein:

said first delay element is configured to generate said pump up signal; and

said second delay element is configured to generate said pump down signal.

14. The apparatus according to claim 11, wherein:

said pump up circuit comprises a first one or more MOSFETs configured to generate said pump up signal; and

said pump up circuit comprises a second one or more MOSFETs configured to generate said pump down signal.

15. The apparatus according to claim 11, wherein:

said pump up circuit is further configured to receive a PMOS source bias; and

said pump down circuit is further configured to receive a NMOS source bias.

16. The apparatus according to claim 11, wherein said output circuit is further configured to receive a PMOS cascode bias and a NMOS cascode bias.

17. The apparatus according to claim 11, wherein said apparatus comprises a reduced static phase error CMOS PLL charge pump.