Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell

• US 6,466,476 B1
• Filed: 01/18/2001
• Issued: 10/15/2002
• Est. Priority Date: 01/18/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Multi Level Memory Technology
• Inventors: Johnsen, Kimberley, Wong, Sau Ching
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/766,272
• Time in Patent Office: 635 Days
• Field of Search: 365/230.01, 365/189.01, 365/189.05, 365/189.12, 365/185.03
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A multi-bit-per-cell non-volatile memory stores different portions of a data stream using different numbers of bits per cell. In particular, data that requires a high degree of data integrity (e.g., the header of a data frame) is stored using a relatively small number of bits per memory cell. Data that is more error-tolerant (e.g., the main data representing music, images, or video) is stored using a relatively large number of bits per memory cell. Write circuitry decodes an input data stream and determines the number of bits to be written in each memory cell. Read circuitry decodes an output data stream and determines a number of bits read from each memory cell to generate the data stream. One such memory includes a decoder in the write circuitry and a decoder in the read circuitry, and another embodiment includes a single decoder that the write and read circuits share. The decoder can include programmable logic array that a user can program according to a protocol used in the data stream to be recorded in and played back from the memory.

Claims

1. A multi-bit-per-cell-memory comprising:

an array of non-volatile memory cells;

a write circuit coupled to the array; and

a decoder coupled to receive a data stream and control the write circuit to write data from the data stream into the array, wherein during a recording operation, the decoder decodes the data stream to identify data types for portions of the data stream, and for each of the portions of the data stream, the decoder selects a number of bits written per memory cell when writing data from that portion, the number of bits per memory cell for any portion of the data stream being selected according to the data type of the portion.

2. The multi-bit-per-cell memory of claim 1, further comprising a read circuit coupled to the array and the decoder, wherein during a playback operation, the decoder:

receives a data stream that the read circuit reads from the array;

decodes the data stream to identify data types for portions of the data stream; and

for each of the portions of the data stream, selects a number of bits to read from each memory cell storing that portion, the number of bits per memory cell for any portion of the data stream being selected according to the data type of the portion.

3. The multi-bit-per-cell memory of claim 2, wherein the decoder comprises programmable array logic that is programmed according to a protocol expected for the data stream.

4. The multi-bit-per-cell memory of claim 3, wherein the protocol is selected from a group consisting of MPEG, JPEG, GIF, and AC-3.

5. The multi-bit-per-cell memory of claim 3, wherein the programmable array logic includes an interface that permits re-programming of the programmable array logic to adapt the multi-bit-per-cell memory to another protocol.

6. The multi-bit-per-cell memory of claim 1, further comprising:

a read circuit coupled to the array and the decoder; and

a second decoder coupled to control the read circuit and receive a second data stream that the read circuit reads from the array, wherein during a playback operation, the second decoder decodes the second data stream to identify data types for portions of the second data stream, and for each of the portions of the second data stream, the second decoder selects a number of bits to read from each memory cell storing that portion, the number of bits per memory cell for any portion of the second data stream being selected according to the data type of the portion.

7. The multi-bit-per-cell memory of claim 1, wherein the decoder comprises programmable array logic that is programmed according to a protocol expected for the data stream.

8. The multi-bit-per-cell memory of claim 7, wherein the protocol is selected from a group consisting of MPEG, JPEG, GIF, and AC-3.

9. The multi-bit-per-cell memory of claim 1, wherein the decoder performs decoding in accordance with a protocol selected from a group consisting of MPEG, JPEG, GIF, and AC-3.

10. The multi-bit-per-cell memory of claim 1, wherein the write circuit is operable in a plurality of modes, each mode corresponding to a different number of bits that the write circuit writes per non-volatile memory cell.

11. The multi-per-cell memory of claim 1, wherein the decoder comprises:

a shift register connected to receive data from the data stream;

data type identification logic coupled to the shift register, the data type identification logic generating a signal that selects a number N from a set of values less than a number M, the number N corresponding to a type for data in the shift register; and

control logic coupled to the shift register and the data type identification logic, wherein in response to the signal indicating the number N, the control logic extracts N bits of data from the shift register and generates a M-bit signal corresponding to the N bits extracted, and wherein

the write circuit writes the N bits to a memory cell by setting a threshold voltage of the memory cell to a level according to the M-bit signal from the control logic.

12. The multi-bit-per-cell memory of claim 11, wherein the data type identification logic is connected to the shift register via programmable array logic.

13. The multi-bit-per-cell memory of claim 12, wherein the programmable array logic is programmed according to a protocol expected for the data stream.

14. The multi-bit-per-cell memory of claim 13, wherein the protocol is selected from a group consisting of MPEG, JPEG, GIF, and AC-3.

15. The multi-bit-per-cell memory of claim 13, wherein the programmable array logic includes an interface that permits re-programming of the programmable array logic to adapt the multi-bit-per-cell memory to another protocol.

16. A multi-bit-per-cell-memory comprising:

an array of non-volatile memory cells;

a read circuit coupled to the array; and

a decoder coupled to control the read circuit and receive a data stream that the read circuit reads from the array, wherein during a playback operation, the decoder decodes the data stream to identify data types for portions of the data stream, and for each of the portions of the data stream, the decoder selects a number of bits extracted from each memory cell storing that portion, the number of bits extracted per memory cell for any portion of the data stream being selected according to the data type of the portion.

17. The multi-bit-per-cell memory of claim 16, wherein the decoder comprises programmable array logic that is programmed according to a protocol expected for the data stream.

18. The multi-bit-per-cell memory of claim 17, wherein the programmable array logic includes an interface that permits re-programming of the programmable array logic to adapt the multi-bit-per-cell memory to another protocol.

19. The multi-bit-per-cell memory of claim 16, wherein the read circuit is operable in a plurality of modes, each mode corresponding to a different number of bits that the read circuit read per non-volatile memory cell.

20. The multi-per-cell memory of claim 16, wherein the read circuit has an M-bit output signal representing a value read from a memory cell, and the decoder comprises:

a shift register;

data type identification logic coupled to the shift register, the data type identification logic generating a signal that selects a number N from a set of values less than M, the number N corresponding to a type for data following data that is in the shift register; and

control logic coupled to the shift register and the data type identification logic, wherein in response to the signal indicating the number N, the control logic converts the M-bit signal to N bits of data and feeds the N bits of data to the shift register.

21. The multi-bit-per-cell memory of claim 20, wherein the data type identification logic is connected to the shift register via programmable array logic.

22. The multi-bit-per-cell memory of claim 21, wherein the programmable array logic is programmed according to a protocol expected for the data stream.

23. The multi-bit-per-cell memory of claim 22, wherein the protocol is selected from a group consisting of MPEG, JPEG, GIF, and AC-3.

24. The multi-bit-per-cell memory of claim 22, wherein the programmable array logic includes an interface that permits re-programming of the programmable array logic to adapt the multi-bit-per-cell memory to another protocol.

25. A recording device for data streams having a protocol, the device comprising:

an array of non-volatile memory cells;

a write circuit coupled to the array; and

a decoder coupled to receive a data stream and control the write circuit to write data from the data stream into the array, wherein during a recording operation, the decoder decodes the data stream according to the protocol to identify data types for portions of the data stream, and for each of the portions of the data stream, the decoder selects a number of bits written per memory cell when writing data from that portion, the number of bits per memory cell for any portion of the data stream being selected according to the data type of the portion.

26. The recording device of claim 25, wherein the decoder comprises programmable array logic that is programmed according to the protocol expected for the data stream.

27. The recording device of claim 26, wherein the programmable array logic includes an interface that permits re-programming of the programmable array logic to adapt the recording device to record a data stream having another protocol.

28. The recording device of claim 25, wherein the protocol is selected from a group consisting of MPEG, jpeg, gif, and AC-3.

29. A playback device for data streams having a protocol, the device comprising:

an array of non-volatile memory cells;

a read circuit coupled to the array; and

a decoder coupled to receive a data stream from the read circuit and to control the read circuit when reading from the array, wherein during a playback operation, the decoder decodes the data stream at least a portion of data stream according to the protocol and identifies data types for subsequent portions of the data stream, and for each of the portions of the data stream, the decoder selects a number of bits read per memory cell when reading data from that portion, the number of bits per memory cell for any portion of the data stream being selected according to the data type of the portion.

30. The playback device of claim 29, wherein the decoder comprises programmable array logic that is programmed according to the protocol expected for the data stream.

31. The playback device of claim 30, wherein the programmable array logic includes an interface that permits re-programming of the programmable array logic to adapt the recording device to record a data stream having another protocol.

32. The recording device of claim 30, wherein the protocol is selected from a group consisting of MP3 and MPEG.

33. A method for recording a data stream in a memory, the method comprising:

decoding the data stream to distinguish a plurality of portions of the data stream and determine corresponding data types for the portions; and

writing each portion of the data stream in a memory, wherein for each portion, writing data from that portion into a memory cell stores in the memory cell exactly N bits of the data, N being a number that depends on the data type corresponding to the portion.

34. The method of claim 33, further comprising inputting the data stream to a decoder integrated in the memory, wherein the decoder performs the decoding and controls the number of bits written per memory cell.

35. The method of claim 34, further comprising programming a programmable logic array in the decoder, wherein the programming enables the decoder to decode a data stream complying with a first standard.

36. The method of claim 35, further comprising re-programming the programmable logic array in the decoder, wherein the re-programming enables the decoder to decode a data stream complying with a second standard.

37. A method for playing back a data stream that was recorded in a memory, the method comprising:

reading a first portion of the data stream from the memory;

decoding the first portion to determine data types of one or more other portions of the data stream stored in the memory;

reading each of the other portions of the data stream from a memory, wherein for each portion, reading data from a memory cell storing data for the portion reads from the memory cell a number of bits that depends on the data type corresponding to the portion.

38. The method of claim 37, wherein reading the first portion of the data stream comprises reading a default number of bits from each memory cell of a plurality of memory cells containing data of the first portion.

39. The method of claim 37, further comprising programming a programmable logic array in the decoder, wherein the programming enables the decoder to decode a data stream complying with a first standard.

40. The method of claim 39, further comprising re-programming the programmable logic array in the decoder, wherein the re-programming enables the decoder to decode a data stream complying with a second standard.