Discontinuity-based memory cell sensing

• US 6,466,498 B2
• Filed: 01/10/2001
• Issued: 10/15/2002
• Est. Priority Date: 01/10/2001
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Hogan, Josh N.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Phung, Anh
• Application Number:
  US09/758,875
• Publication Number:
  US 20020089869A1
• Time in Patent Office: 643 Days
• Field of Search: 365/206, 365/105, 365/96, 365/175, 365/225.7
• US Class Current: 365/206
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/36 using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode

Abstract

Systems and methods that enable the state of a memory cell to be determined with greater accuracy are described. In one memory cell sensing approach, a memory cell is addressed, an input signal is applied to the addressed memory cell over a range of values, and the state of the memory cell is read based upon a discontinuity in a sensed electrical response to the applied input signal values.

Claims

1. A method of reading a memory cell in a memory cell array comprising:

addressing a memory cell;

applying to the addressed memory cell an input signal over a range of values; and

reading the state of the memory cell based upon a discontinuity in a sensed electrical response to the applied input signal values.

2. The method of claim 1, wherein the state of the memory cell is read based upon a discontinuity in the sensed electrical response over a range of applied input signal values encompassing a rail voltage value.

3. The method of claim 2, wherein the state of the memory cell is read based upon a discontinuity in the sensed electrical response over a range of applied input signal values on the order of one or more diode drops of the rail voltage value.

4. The method of claim 1, wherein the state of the memory cell is read based upon a discontinuity in direction of the sensed electrical response.

5. The method of claim 1, wherein the state of the memory cell is read based upon a discontinuity in slope of the sensed electrical response.

6. The method of claim 1, wherein the state of the memory cell is read based upon the presence or absence of a discontinuity in an electrical response to the applied input signal.

7. The method of claim 1, further comprising reading the state of the memory cell multiple times within a read period.

8. The method of claim 7, further comprising applying a noise immunity process to the multiple memory cell readings.

9. The method of claim 8, wherein the noise immunity process comprises an integrate and dump process.

10. The method of claim 1, wherein an electrical response to an applied row signal is sensed and an electrical response to an applied column signal is sensed.

11. The method of claim 10, further comprising applying a common mode rejection noise immunity process to the sensed electrical responses to the applied row and column signals.

12. A system for reading a memory cell in a memory cell array, comprising:

a control circuit configured to address a memory cell, apply to the memory cell an input signal over a range of values and read the state of the memory cell based upon a discontinuity in a sensed electrical response to the applied input signal values.

13. The system of claim 12, wherein the state of the memory cell is read based upon a discontinuity in the sensed electrical response over a range of applied input signal values encompassing a rail voltage value.

14. The system of claim 13, wherein the state of the memory cell is read based upon a discontinuity in the sensed electrical response over a range of applied input signal values on the order of one or more diode drops of the rail voltage value.

15. The system of claim 12, wherein the state of the memory cell is read based upon a discontinuity in direction of the sensed electrical response.

16. The system of claim 12, wherein the memory cell is sensed based upon a discontinuity in slope of the sensed electrical response.

17. The system of claim 12, wherein the state of the memory cell is read based upon the presence or absence of a discontinuity in an electrical response to the applied input signal.

18. The system of claim 12, wherein the control circuit is configured to read the state of the memory cell multiple times within a read period.

19. The system of claim 18, wherein the control circuit is configured to apply a noise immunity process to the multiple memory cell readings.

20. The system of claim 12, wherein the control circuit is configured to apply a common mode rejection noise immunity process to sensed electrical responses to an applied row signal and an applied column signal.