Built-in AC self test using pulse generators

• US 6,466,520 B1
• Filed: 02/05/1999
• Issued: 10/15/2002
• Est. Priority Date: 09/17/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chung, Daniel Y., Ferguson, David L., Conn, Robert O., Wells, Robert W., Patrie, Robert D., Speyer, Gil A.
• Primary Examiner(s): MISKA, VIT W
• Application Number:
  US09/244,753
• Time in Patent Office: 1,348 Days
• Field of Search: 368/113, 368/118-120, 324/617, 324/763, 324/765, 324/73.AT, 327/265, 331/57
• US Class Current: 368/118
• CPC Class Codes: G01R 27/04 in circuits having distributed constants , e.g. having very long conductors or involving high frequencies
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

Claims

1. A phase discriminator for producing a test clock signal having a period determined by a signal-propagation time required for one of a low-to-high signal transition and a high-to-low signal transition to traverse a test circuit from a test-circuit input node to a test-circuit output node, the phase discriminator comprising:

a. a pulse generator having a pulse-generator output node connected to the test-circuit input node, the pulse generator configured to provide the test-circuit input node with a pulse; and

b. a phase detector having a phase-detector input node connected to the test-circuit output node and a phase-detector output node connected to the pulse-generator, the phase-detector input node adapted to receive a delayed version of the pulse;

i. wherein the low-to-high signal transitions of the delayed version of the pulse are delayed by the first signal-propagation time required for low-to-high signal transitions to traverse the test circuit; and

ii. wherein the high-to-low signal transitions of the delayed version of the pulse are delayed by a second signal-propagation time required for a high-to-low signal transition to traverse the test circuit.

2. The phase discriminator of claim 1, wherein the phase-detector output node is configured to provide a periodic output signal having a period defined by the propagation delay time of low-to-high transitions through the test circuit, and further wherein the period is independent of the signal propagation delay of high-to-low transitions through the test circuit.

3. The phase discriminator of claim 1, further comprising a selective inverter having an input node connected to the output node of the phase discriminator and an output node connected to the input node of the test circuit.

4. The phase discriminator of claim 1, further comprising a selective inverter having an input node connected to the output node of the phase discriminator and an output node connected to the input node of the test circuit.

5. The phase discriminator of claim 1, further comprising a counter having an input node connected to the second output node of the phase detector.

6. An oscillator sequentially producing alternating low-to-high and high-to-low signal transitions, the oscillator comprising:

a. a test circuit adapted to receive the signal transitions on a test-circuit input node and to output corresponding signal transitions on a test-circuit output node, wherein the test circuit delays the high-to-low signal transitions by a first delay period and delays the low-to-high signal transitions by a second delay period;

b. a phase discriminator having;

i. a phase-discriminator input node connected to the test-circuit output node; and

ii. a phase-discriminator output node connected to the test-circuit input node;

iii. wherein the phase discriminator is configured to produce a clock transition on the phase-discriminator discriminator output node in response to each high-to-low signal transition; and

iv. wherein the phase discriminator is further configured to ignore each low-to-high signal transition; and

c. a counter having a counter input terminal connected to the second output node of the phase discriminator, the counter configured to count the number of clock transitions.

7. A system for sequentially producing alternating signal transitions of first and second opposite polarities, the system comprising:

a. a test circuit adapted to receive the signal transitions on a test-circuit input node and to output corresponding signal transitions on a test-circuit output node;

b. a phase discriminator having;

i. an input node connected to the test-circuit output node;

ii. a first output node connected to the test-circuit input node; and

iii. a second output node;

iv. wherein the phase discriminator is configured to produce an output signal on the first output node in response to each signal transition of only one of the first and second polarities, thereby producing a periodic series of clock transitions; and

c. a counter having a counter input terminal connected to the second output node of the phase discriminator, the counter configured to count the number of clock transitions.

8. A phase discriminator for measuring a first signal-propagation time required for a low-to-high signal transition to traverse a test circuit from an input node of the test circuit to an output node of the test circuit, the phase discriminator comprising:

a. a pulse generator having an input node and an output node, the pulse generator configured to provide the test-circuit input node with a test pulse in response to a signal transition on the pulse-generator input node; and

b. a phase detector having an output node connected to the pulse-generator input node and an input node connected to the test-circuit output node;

c. wherein the phase detector is adapted to initiate the signal transition to the pulse-generator input node in response to only one of a high-to-low or low-to-high signal transition from the test-circuit output node.

9. The phase discriminator of claim 8, further comprising counter having an input node connected to the output node of the phase detector.

10. The phase discriminator of claim 8, further comprising a selective inverter having an input node connected to the output node of the pulse generator and an output node connected to the input node of the test circuit.

11. The phase discriminator of claim 8, further comprising a selective inverter having an input node connected to the output node of the test circuit and an output node connected to the input node of the phase detector.

12. A test circuit formed in an FPGA, the test circuit comprising:

a. a closed loop formed from the following elements connected in order;

i. a pulse generator;

ii. a first optional inverter;

iii. a test circuit; and

iv. a second optional inverter;

b. means for controlling the optional inverters; and

c. a counter for counting pulses passed through the closed loop.

13. The test circuit of claim 12 wherein the pulse generator comprises:

a. A flip-flop providing an output signal; and

b. a one-shot circuit receiving the output signal of the flip-flop and generating a pulse in response to a change of state of the output signal.

14. The test circuit of claim 12 wherein the pulse generator comprises:

a. a first flip-flop providing a first flip-flop output signal;

b. a second flip-flop receiving on its input terminal the first flip-flop output signal and having a second flip-flop clock terminal; and

c. means for applying a signal from an intermediate point of the test circuit to the second flip-flop clock terminal.

15. A test circuit formed in an FPGA, the test circuit comprising:

a. a test path formed in the FPGA, for which delay is to be determined;

b. means for generating a test pulse to be passed through the test path in response to receiving one of a rising and falling edge of a previous test pulse passed through the test path;

c. means for optionally inverting the test pulse before and after it is passed through the test path; and

d. a counter for counting transitions on the test path.

16. A test circuit formed in an FPGA, the test circuit comprising:

a. a test path for which delay is to be determined;

b. means for starting a pulse to be passed through the test path;

c. means for selecting whether the pulse is a positive pulse or a negative pulse;

d. a multiplexer having a plurality of input terminals for receiving the pulse at a plurality of positions on the test path and having an output terminal for providing a delayed pulse;

e. means for ending the pulse in response to the delayed pulse; and

f. a counter for counting transitions on the test path.