Delay locked loop based circuit for data communication

• US 6,466,615 B1
• Filed: 12/30/1999
• Issued: 10/15/2002
• Est. Priority Date: 12/30/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Song, Hongjiang
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Ha, Dac V.
• Application Number:
  US09/475,486
• Time in Patent Office: 1,020 Days
• Field of Search: 375/229, 375/230, 375/232, 375/233, 375/245, 375/247, 375/340, 375/346, 375/348, 375/350, 708/300, 708/313, 708/316, 708/322, 708/323, 341/129, 341/141, 341/142, 341/159, 341/164, 341/165, 341/168, 341/169
• US Class Current: 375/232
• CPC Class Codes: H03H 17/04 Recursive filters
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference

Abstract

An apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

Claims

1. An apparatus comprising:

a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output;

a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response; and

a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

2. The apparatus of claim 1, wherein the input signal is an analog signal and a different threshold signal is associated with each quantizer and comprises a value selected to be within the range of the input signal.

3. The apparatus of claim 2, wherein the different threshold signals are equally spaced within the range of the input signal.

4. The apparatus of claim 2, wherein each of the plurality of quantizers comprises a comparator that subtracts the threshold signal from the input signal to generate a representative digital output corresponding to whether the threshold signal is greater than or less than the input signal.

5. The apparatus of claim 4, wherein the representative digital output is a high when the threshold signal is less than the input signal.

6. The apparatus of claim 2, further comprising a delay line having a plurality of flip-flops configured sequentially where each of the plurality of flip flops delays the multiplexer output one clock cycle.

7. The apparatus of claim 6, wherein the MAC unit multiplies each delayed output by a coefficient c_n, where n is the number of flip flops representative of the frequency response.

8. The apparatus of claim 7, wherein the coefficients c_n are determined by the equation:

$c_n=\frac{a_n}{v_{\mathrm{th}}}$

where a_n represents an order coefficient representative of the frequency response, n represents the order of the frequency response and v_th the selected threshold signal.

9. The apparatus of claim 7, wherein the MAC unit generates an output from the sum of all the delayed outputs multiplied by their respective coefficients, c_n.

10. The apparatus of claim 9, wherein the multiplexer selects one of the plurality of quantizer outputs according to the output generated from the MAC unit.

11. The apparatus of claim 1, wherein the output sequence generated by the MAC unit based on a previously selected one of the quantizer outputs according to the frequency response, can be represented by the equation:

12. A method for generating an output from an infinite impulse response (IIR) filter comprising:

configuring a plurality of quantizers to compare a selected threshold signal with an input signal and generate an output;

selecting one of a plurality of quantizer outputs according to a frequency response; and

generating a selection output to select one of the plurality of quantizer outputs based on a previously selected one of the quantizer outputs according to the frequency response.

13. The method of claim 12, further comprising:

configuring the plurality of quantizers to subtract the threshold signal from the input signal to generate a representative digital output corresponding to whether the threshold signal is greater than or less than the input signal.

14. The method of claim 12, wherein generating a selection output comprises delaying the selected one of the plurality of quantizers outputs, generated from the multiplexer, by at least one cycle.

15. The method of claim 14, wherein generating a selection output comprises multiplying the delayed output by a coefficient c_n where n is a selected order of the frequency response.

16. The method of claim 14, wherein generating a selection output further comprises accumulating as a sum all of the delayed outputs multiplied by their respective coefficients.

17. A communication system comprising:

a first communication terminal coupled to provide information carried by an input signal;

a communication link coupled to the first communication terminal;

a second communication terminal coupled to provide the input signal from said first communication terminal via said communication link, the second communication terminal comprising a filter, which converts the input signal into digital baseband data comprising;

a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output;

a multiplexer that selects one of the plurality of quantizer outputs according to a frequency response; and

a multiplication-accumulation (MAC) unit that generates an output based on a previously selected one of the quantizer outputs according to the frequency response.