Radio frequency data communications device

• US 6,466,634 B1
• Filed: 09/28/1998
• Issued: 10/15/2002
• Est. Priority Date: 05/13/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ovard, David K., Tuttle, John R., Rotzoll, Robert R., Tuttle, Mark E., Lowrey, Tyler, Higgins, Brian P., Yu, Shu-Sun, Devereaux, Kevin M., Pax, George E., OʼToole, James E.
• Primary Examiner(s): Holloway, III, Edwin C.
• Application Number:
  US09/161,512
• Time in Patent Office: 1,478 Days
• Field of Search: 375/374, 375/298, 375/376, 332/128, 332/103, 307/498, 340/10.4, 342/42, 342/44, 342/51, 327/244, 327/108, 331/1.A
• US Class Current: 375/374
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0712 the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier active means for hindering electromagnetic reading or writing G06K19/07336
• CPC Class Codes: G06K 19/0716 at least one of the integrated circuit chips comprising a sensor or an interface to a sensor
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/0726 the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10059 transponder driven
• CPC Class Codes: H01Q 1/2225 used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider

Abstract

A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Claims

1. CMOS transmitter carrier circuitry, the circuitry receiving a digital clock signal, the circuitry comprising:

a phase locked loop including a voltage controlled oscillator configured to multiply the frequency of the digital clock signal by a predetermined multiple, a loop filter coupled to the voltage controlled oscillator, and a phase-frequency detector and charge pump coupled to the voltage controlled oscillator and to the loop filter to maintain a desired frequency, the phase locked loop having an output providing a transmitter carrier; and

divider circuitry having an input coupled to the voltage controlled oscillator and receiving the multiplied frequency, the divider circuitry being configured to divide by the predetermined multiple, and the divider circuitry having an output coupled to the phase-frequency detector.

2. CMOS transmitter carrier circuitry in accordance with claim 1 wherein the loop filter is a passive loop filter.

3. CMOS transmitter carrier circuitry in accordance with claim 1 wherein the voltage controlled oscillator has a plurality of outputs that are configured to be angularly spaced apart with respect to phase.

4. CMOS transmitter carrier circuitry in accordance with claim 3 and further comprising a frequency doubler that receives at least some of the angularly spaced apart outputs of the voltage controlled oscillator, and that is configured to produce a signal with a frequency that is double the frequency of the outputs of the voltage controlled oscillator.

5. CMOS transmitter carrier circuitry in accordance with claim 4 wherein the frequency doubler comprises first and second Gilbert cells coupled together, a frequency generator configured to apply a first sinusoidal wave to the first Gilbert cell, and a phase shifter coupled between the first and second Gilbert cells to apply to the second Gilbert cell a sinusoidal wave that is shifted from the first sinusoidal wave.

6. CMOS transmitter carrier circuitry in accordance with claim 1, wherein the charge pump comprises:

a first charge pump coupled to a start-up circuit and configured to pump a frequency of the voltage controlled oscillator up in coarse, medium or medium fine steps in response to a start-up command from the start-up circuit; and

a second charge pump coupled to the phase-frequency detector and configured to pump up or down the frequency of the voltage controlled oscillator in fine steps in response to signals from the phase-frequency detector.

7. CMOS transmitter carrier circuitry in accordance with claim 6, wherein the start-up circuit is configured to initially invoke coarse or medium steps to pump up the frequency of the voltage controlled oscillator and is configured to invoke medium fine or fine steps when the start-up circuit determines that the frequency of the voltage controlled oscillator is within a few percent of a desired frequency.

8. A CMOS transmitter receiving a digital clock signal, the transmitter comprising:

a phase locked loop including a voltage controlled oscillator multiplying the frequency of the digital clock signal by a predetermined multiple, a passive loop filter, and a phase-frequency detector and charge pump coupled to the voltage controlled oscillator and to the loop filter to maintain a desired frequency, the voltage controlled oscillator having a plurality of outputs that are angularly spaced apart with respect to phase, the phase locked loop having an output providing a transmitter carrier;

divider circuitry having an input coupled to one of the outputs of the voltage controlled oscillator, the divider circuitry being configured to divide by the predetermined multiple and having an output coupled to the phase-frequency detector; and

a modulator coupled to the phase locked loop to use the transmitter carrier.

9. A CMOS transmitter in accordance with claim 8 wherein the voltage controlled oscillator has outputs that are spaced apart, with respect to phase in 45 degree intervals.

10. A CMOS transmitter in accordance with claim 9 wherein the predetermined multiple is sixteen.

11. A CMOS transmitter in accordance with claim 8, wherein the charge pump comprises:

a first charge pump coupled to a start-up circuit and configured to pump a frequency of the voltage controlled oscillator up in coarse, medium or medium fine steps in response to a start-up command from the start-up circuit; and

a second charge pump coupled to the phase-frequency detector and configured to pump up or down the frequency of the voltage controlled oscillator in fine steps in response to signals from the phase-frequency detector.

12. A CMOS transmitter in accordance with claim 11, wherein the start-up circuit is configured to initially invoke coarse or medium steps to pump up the frequency of the voltage controlled oscillator and is configured to invoke medium fine or fine steps when the start-up circuit determines that the frequency of the voltage controlled oscillator is within a few percent of a desired frequency.

13. An integrated circuit including carrier circuitry for providing a carrier for wireless communications, the carrier circuitry receiving a digital clock signal, the carrier circuitry being defined by CMOS circuit elements, the carrier circuitry comprising:

a phase locked loop including a voltage controlled oscillator multiplying the frequency of the digital clock signal by a predetermined multiple, a loop filter, a phase-frequency detector receiving the digital clock signal and comparing the frequency and phase of the digital clock signal with a second signal and configured to issue pump up or pump down signals in response to the comparison, and a charge pump coupled to the phase-frequency detector, and to the loop filter to maintain a desired frequency in response to the pump up and pump down signals, the charge pump being configured to receive the pump up and pump down signals and produce an output having a voltage that varies in response to the pump up and pump down signals, the voltage controlled oscillator having an output, the phase locked loop having an output providing a transmitter carrier; and

divider circuitry having an input coupled to the output of the voltage controlled oscillator, the divider circuitry being configured to divide by the predetermined multiple and having an output defining the second signal coupled to the phase-frequency detector.

14. An integrated circuit in accordance with claim 13 wherein the frequency of the output of the voltage controlled oscillator is configured to vary depending on a voltage provided by the loop filter to the voltage controlled oscillator.

15. An integrated circuit in accordance with claim 14 wherein the loop filter is configured to filter the output of the charge pump.

16. An integrated circuit in accordance with claim 13 wherein the predetermined multiple is sixteen.

17. An integrated circuit in accordance with claim 13, wherein the charge pump comprises:

a first charge pump coupled to a start-up circuit and configured to pump a frequency of the voltage controlled oscillator up in coarse, medium or medium fine steps in response to a start-up command from the start-up circuit; and

a second charge pump coupled to the phase-frequency detector and configured to pump up or down the frequency of the voltage controlled oscillator in fine steps in response to signals from the phase-frequency detector.

18. An integrated circuit in accordance with claim 17, wherein the start-up circuit is configured to initially invoke coarse or medium steps to pump up the frequency of the voltage controlled oscillator and is configured to invoke medium fine or fine steps when the start-up circuit determines that the frequency of the voltage controlled oscillator is within a few percent of a desired frequency.

19. An integrated circuit including carrier circuitry for providing a carrier for wireless communications, the carrier circuitry receiving a digital clock signal, the carrier circuitry being defined by CMOS circuit elements, the carrier circuitry comprising:

a phase locked loop including a voltage controlled oscillator multiplying the frequency of the digital clock signal by a predetermined multiple, a passive loop filter, a phase-frequency detector receiving the digital clock signal and comparing the frequency and phase of the digital clock signal with a second signal and configured to issue pump up or pump down signals in response to the comparison, and a charge pump coupled to the phase-frequency detector, to the voltage controlled oscillator, and to the loop filter to maintain a desired frequency in response to the pump up and pump down signals, the voltage controlled oscillator having a plurality of outputs that are angularly spaced apart with respect to phase, the phase locked loop having an output providing a transmitter carrier; and

divider circuitry having an input coupled to one of the outputs of the voltage controlled oscillator, the divider circuitry dividing by the predetermined multiple and having an output defining the second signal coupled to the phase-frequency detector.

20. An integrated circuit in accordance with claim 19 wherein the predetermined multiple is sixteen.

21. An integrated circuit in accordance with claim 20 and further comprising a frequency doubler that receives at least some of the angularly spaced apart outputs of the voltage controlled oscillator, and that is configured to produce a signal with a frequency that is double the frequency of the outputs of the voltage controlled oscillator.

22. An integrated circuit in accordance with claim 21 and further comprising a second frequency doubler coupled to the first mentioned frequency doubler and that is configured to produce a signal with a frequency that is double the frequency of the signal produced by the first frequency doubler.

23. An integrated circuit in accordance with claim 20 and further comprising a first frequency doubler stage including a first frequency doubler that receives at least some of the angularly spaced apart outputs of the voltage controlled oscillator, and that is configured to produce a signal with a frequency that is double the frequency of the outputs of the voltage controlled oscillator, and a second frequency doubler that receives other of the angularly spaced apart outputs of the voltage controlled oscillator, and that is configured to produce a signal with a frequency that is double the frequency of the outputs of the voltage controlled oscillator.

24. An integrated circuit in accordance with claim 23 and further comprising a second frequency doubler stage coupled to the first frequency doubler stage and that is configured to produce a signal with a frequency that is double the frequency of the signals produced by the first frequency doubler stage.

25. An integrated circuit in accordance with claim 20, wherein the charge pump comprises:

a first charge pump coupled to a start-up circuit and configured to pump a frequency of the voltage controlled oscillator up in coarse, medium or medium fine steps in response to a start-up command from the start-up circuit; and

a second charge pump coupled to the phase-frequency detector and configured to pump up or down the frequency of the voltage controlled oscillator in fine steps in response to signals from the phase-frequency detector.

26. An integrated circuit in accordance with claim 25, wherein the start-up circuit is configured to initially invoke coarse or medium steps to pump up the frequency of the voltage controlled oscillator and is configured to invoke medium fine or fine steps when the start-up circuit determines that the frequency of the voltage controlled oscillator is within a few percent of a desired frequency.

27. An integrated circuit including a transmitter for wireless communications, the transmitter receiving a digital clock signal, the transmitter being defined by CMOS circuit elements, the transmitter comprising:

a phase locked loop including a voltage controlled oscillator multiplying the frequency of the digital clock signal by a predetermined multiple, a passive loop filter, a phase-frequency detector receiving the digital clock signal and comparing the frequency and phase of the digital clock signal with a second signal and configured to issue pump up or pump down signals in response to the comparison, and a charge pump coupled to the phase-frequency detector, the voltage controlled oscillator and to the loop filter to maintain a desired frequency in response to the pump up and pump down signals, the voltage controlled oscillator having a plurality of outputs that are angularly spaced apart with respect to phase, the phase locked loop having an output providing a transmitter carrier;

divider circuitry having an input coupled to one of the outputs of the voltage controlled oscillator, the divider circuitry dividing by the predetermined multiple and having an output defining the second signal coupled to the phase-frequency detector; and

a modulator coupled to the voltage controlled oscillator.

28. An integrated circuit in accordance with claim 27 wherein the voltage controlled oscillator includes a plurality of stages, one of the stages including a first transistor having a control electrode defining a first input, and first and second power electrodes, wherein the first power electrode defines a first node, wherein the stage further includes a second transistor having a control electrode defining a second input, and having first and second power electrodes, wherein the first power electrode of the second transistor defines a second node, wherein the stage further includes a current source connected to the second power electrodes of the first and second transistors, the current source being configured to direct current away from the second power electrodes of the first and second transistors, and wherein the stage further includes a variable resistance configured to couple the first and second nodes to a supply voltage.

29. An integrated circuit in accordance with claim 27, wherein the charge pump comprises:

a first charge pump coupled to a start-up circuit and configured to pump a frequency of the voltage controlled oscillator up in coarse, medium or medium fine steps in response to a start-up command from the start-up circuit; and

a second charge pump coupled to the phase-frequency detector and configured to pump up or down the frequency of the voltage controlled oscillator in fine steps in response to signals from the phase-frequency detector.

30. An integrated circuit in accordance with claim 29, wherein the start-up circuit is configured to initially invoke coarse or medium steps to pump up the frequency of the voltage controlled oscillator and is configured to invoke medium fine or fine steps when the start-up circuit determines that the frequency of the voltage controlled oscillator is within a few percent of a desired frequency.