Cipher processor, IC card and cipher processing method

• US 6,466,669 B1
• Filed: 12/31/1998
• Issued: 10/15/2002
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Matsui, Mitsuru, Tokita, Toshio
• Primary Examiner(s): BARRON JR, GILBERTO
• Application Number:
  US09/214,271
• Time in Patent Office: 1,384 Days
• Field of Search: 380/37, 380/29
• US Class Current: 380/37
• CPC Class Codes: H04L 2209/122 Hardware reduction or efficient architectures
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

Abstract

The present invention can be applied to a cipher processing apparatus, which includes a function F having a configuration of repeating process and inside of the function F, a function f having a configuration of repeating process is included. According to the invention, the cipher processing apparatus is configured by registers 301 through 303 for temporarily holding data, selectors A through C, 311 through 313, and a function f operating circuit 323 for transforming data. An output data from the function f operating circuit 323 is held in the register C 303, and the selector C 313 selects either to repeat the data transformation by the function operating circuit 323 or not. When a cipher processing apparatus includes a function F having a configuration of repeating process and inside of the function F, a function f having a configuration of repeating process is included, the cipher processing apparatus can be embodied efficiently, which enables to reduce the circuit scale and to save electric power.

Claims

1. A cipher processing apparatus performing a first data transformation process on an input data a plurality of times by a first operating circuit, wherein:

the first operating circuit comprises a loop processing circuit for performing a second data transformation process a plurality of times;

wherein the loop processing circuit comprises a second operating circuit, a data holding circuit, and a selecting circuit to form a processing loop;

wherein the second operating circuit performs the second data transformation process;

the data holding circuit tentatively holds the data on which the second data transformation process was performed; and

the selecting circuit selects either to terminate or to continue the second data transformation process by the loop processing circuit;

wherein said second operating circuit comprises;

a data dividing circuit dividing data input to the second operating circuit into a first divided data and a second divided data;

a third operating circuit transforming the first divided data;

an XOR circuit XORing an output data from the third operating circuit with the second divided data bit by bit; and

a data uniting circuit uniting an output data from the XOR circuit and the second divided data.

2. The cipher processing apparatus of claim 1, wherein the selecting circuit inputs a data for the first data transformation process by the first operating circuit and a data held in the data holding circuit, and the selecting circuit selects the data held in the data holding circuit when a process by the loop processing circuit is to be continued.

3. The cipher processing apparatus of claim 2, wherein the selecting circuit selects the data for the first data transformation process by the first operating circuit when a process by the processing loop circuit starts.

4. The cipher processing apparatus of claim 3, further comprising:

a register A and a register B alternately holding the data for the first data transformation by the first operating circuit;

two XOR circuits XORing bit by bit the data on which the first data transformation was performed by the first operating circuit with the data held in the register A and with the data held in the register B, respectively;

a selector A and a selector B selecting one of the data on which the first data transformation was performed by a first operating unit and an XORed data by the XOR circuit to hold in the register A and the register B, respectively; and

wherein the selecting circuit alternately selects the register A and the register B to start the process of the loop processing circuit.

5. The cipher processing apparatus of claim 1, wherein the first operating circuit further performs a data transformation different from the second data transformation process for the data on which the second data transformation was performed by a processing loop unit to output a transformed data.

6. The cipher processing apparatus of claim 1, wherein the second operating circuit comprises:

m (m≧

1) number of function operating circuits inputting identical data from the selecting circuit; and

a selector with m inputs and one output for inputting data operated by the m number of function operating circuits and selecting one of the input data.

7. The cipher processing apparatus of claim 1, further comprising:

a function operating unit transforming data output from the selecting circuit; and

a selector inputting data operated by the function operating unit and the data output from the selecting circuit, and outputting one of the data.

9. An IC (integrated circuit) card communicating data with a reader/writer, wherein the data is encrypted/decrypted by the cipher processing apparatus of claim 1, the IC card comprising:

a data receiving circuit receiving the data from the reader/writer; and

a data transmitting circuit transmitting the data to the reader/writer.

10. An IC card communicating data with a reader/writer, wherein the data is encrypted/decrypted by the cipher processing apparatus of claim 1, the IC card comprising:

a data receiving circuit receiving the data from the reader/writer; and

a data transmitting circuit transmitting the data to the reader/writer.

8. A cipher processing method performing a first data transformation for an input data a plurality of times by a first operating step, wherein:

the first operating step comprises a loop processing step performing a second data transformation at a plurality of times;

wherein the loop processing step comprises;

a second operating step performing the second data transformation;

a data holding step temporarily holding data on which the second data transformation was performed; and

a selecting step for selecting either to terminate or to continue the second data transformation by the loop processing step;

wherein the second operating step comprises;

a data dividing step dividing data input to the second operating step into a first divided data and a second divided data;

a third operating step transforming the first divided data;

an XOR step XORing an output data from the third operating step with the second divided data bit by bit; and

a data uniting step uniting an output data from the XOR step and the second divided data.

11. A cipher processing apparatus for inputting data A and data B to be encrypted,

having a first operating unit for alternately performing a first data transformation on the data A and the data B;

and a second operating unit for performing a second data transformation on one of the data A and the data B input to the first operating unit inside of the first operating unit,

encrypting the data A and the data B by repeatedly operating the second operating unit inside of the first operating unit and by repeatedly operating the first operating unit, and

outputting an encrypted data A and an encrypted data B,

the cipher processing apparatus comprising;

a register A for inputting and holding the data A to be encrypted, holding and outputting the data A to be input to the first operating unit, and outputting the encrypted data A after repeatedly operating the first operating unit;

a register B for inputting and holding the data B to be encrypted, holding and outputting the data B to be input to the first operating unit, and outputting the encrypted data B after repeatedly operating the first operating unit;

a register C, provided inside of the first operating unit, for repeatedly holding and outputting the data C output from the second operating unit;

a selector C for selecting one of the register A, the register B and the register C, and outputting the data held in the register selected;

an XOR circuit A for XORing the data output by the selector C with the data A held in the register A;

a selector A for selecting a result XORed by the XOR circuit A, outputting the result to the register A to make the register A hold the result;

an XOR circuit B for XORing the data output by the selector C with the data B held in the register B; and

a selector B for selecting a result XORed by the XOR circuit B, outputting the result to the register B to make the register B hold the result,

wherein the first operating unit includes the second operating unit, the register C and the selector C;

wherein the second operating unit, the register C and the selector C form a first processing loop inside of the first operating unit for repeatedly performing the second data transformation by the second operating unit; and

wherein the first operating unit forms the second processing loop with the XOR circuits A and B, the selectors A and B, and the registers A and B for repeatedly performing the first data transformation by the first operating unit;

wherein the second operating unit inputs the data output from the selector C, performs the second data transformation on the data, outputs the data to the register C to make the register C hold the data as data C;

wherein the selector C alternately selects the data A held in the register A and the data B held in the register B to output to the second operating unit to make the first operating unit repeatedly perform the first data transformation alternately on the data A and the data B with making the second operating unit start repeatedly performing the second data transformation in case of repeatedly operating the first operating unit;

the selector C selects the data C held in the register C to output to the second operating unit to make the second operating unit repeatedly perform the second data transformation in case of repeatedly performing the second data transformation by the second operating unit; and

the selector C selects the data C held in the register C to output to the XOR circuits A and B, and makes the XOR circuits A and B XOR in case of terminating the second data transformation by the second operating unit being performed repeatedly,

wherein the selectors A and B alternately select the result XORed by the XOR circuit A and the result XORed by the XOR circuit B and output the result to the registers A and B, and make the registers A and B alternately hold the result in case of terminating the second data transformation by the second operating unit being performed repeatedly.

13. The cipher processing apparatus according to claim 11, wherein the second operating unit comprises:

a data dividing unit for dividing the data input to the second operating unit into a first divided data and a second divided data;

a third operating unit for transforming the first divided data;

an XOR unit for XORing an output data of the third operating unit with the second divided data bit by bit; and

a data uniting unit for uniting an output data of the XOR unit and the second divided data.

14. An IC card for communicating data with a reader/writer comprising:

a data receiving unit for receiving the data from the reader/writer;

a data transmitting unit for transmitting the data to the reader/writer; and

a cipher processing apparatus according to claim 13 for encrypting the data.

12. A cipher processing apparatus for inputting data A and data B to be encrypted;

having a first operating unit for alternately performing a first data transformation on the data A and the data B; and

a second operating unit for performing a second data transformation on one of the data A and the data B input to the first operating unit inside of the first operating unit;

encrypting the data A and the data B by repeatedly operating the second operating unit inside of the first operating unit and by repeatedly operating the first operating unit, and

outputting an encrypted data A and an encrypted data B

the cipher processing apparatus comprising;

an input line A for inputting the data A to be encrypted, an input line B for inputting the data B to be encrypted, an output line A for outputting the encrypted data A; and

an output line B for outputting the encrypted data B;

registers A, B and C for holding data;

selectors A, B and C for selecting data;

XOR circuits A and B;

wherein the first operating unit includes the selector C and the register C and the second operating unit;

wherein the register A is connected to an output side of the selector A, and also connected to the output line A for outputting the data A, an input side of the selector C and an input side of the XOR circuit A;

wherein the register B is connected to an output side of the selector B, and also connected to the output line B for outputting the data B, an input side of the selector C and an input side of the XOR circuit B;

wherein the selector A is connected to the input line A for inputting the data A and an output side of the XOR circuit A, and also connected to an input side of the register A; and

the selector A inputs the data A from the input line A and outputs the data A to make the register A hold the data A in case of initiating a first operation of the first operating unit;

wherein the selector B is connected to the input line B for inputting the data B and the output side of the XOR circuit B, and also connected to an input side of the register B; and

the selector B inputs the data B from the input line B and outputs the data B to make the register B hold the data B in case of initiating the first operation of the first operating unit;

wherein the selector C is connected to an output side of the register A, an output side of the register B and an output side of the register C, and also connected to an input side of the second operating unit, an input side of the XOR circuit A and an input side of the XOR circuit B;

wherein the second operating unit is connected to an output side of the selector C, and also connected to an input side of the register C; and

the second operating unit performs the second data transformation on the data selected by the selector C and outputs a result of the second data transformation to make the register C hold the result as data C;

wherein the register C is connected to an output side of the second operating unit, and also connected to an input side of the selector C;

wherein the XOR circuit A is connected to an output side of the selector C and an output side of the register A, and also connected to an input side of the selector A;

the XOR circuit A XORs the data C output from the selector C with the data A held in the register A and outputs an XORed result to the selector A;

wherein the XOR circuit B is connected to an output side of the selector C and an output side of the register B, and also connected to an input side of the selector B;

the XOR circuit B XORs the data C output from the selector C with the data B held in the register B and outputs an XORed result to the selector B;

wherein the selector C selects the data A held in the register A and outputs the data A to the second operating unit, the XOR circuit A and the XOR circuit B in case of initiating an odd-numbered operation of the first operating unit;

the selector C selects the data B held in the register B and outputs the data B to the second operating unit, the XOR circuit A and the XOR circuit B in case of initiating an even-numbered operation of the first operating unit; and

the selector C selects the data C held in the register C and outputs the data C to the second operating unit, the XOR circuit A and the XOR circuit B in case of repeatedly operating the second operating unit or terminating the second operating unit being operated repeatedly; and

wherein the selector A does not select the result XORed by the XOR circuit A to make the register A hold the data A as it is in case of terminating the odd-numbered operation of the first operating unit; and

the selector A selects the result XORed by the XOR circuit A to make register A hold the result as the data A in case of terminating the even-numbered operation of the first operating unit;

wherein the selector B does not select the result XORed by the XOR circuit B to make the register B hold the data B as it is in case of terminating the even-numbered operation of the first operating unit; and

the selector B selects the result XORed by the XOR circuit B to make register B hold the result as the data B in case of terminating the odd numbered operation of the first operating unit.

15. A cipher processing method implemented by a cipher processing apparatus having registers A, B, C, selectors A, B, C, and XOR circuits A and B,

inputting data A and data B to be encrypted;

having a first operating step for alternately performing a first data transformation on the data A and the data B;

having a second operating step, provided in the first operating step, for performing a second data transformation on the data A or the data B input to the first operating step;

encrypting the data A and the data B by repeatedly operating the second operating step inside of the first operating step and by repeatedly operating the first operating step;

outputting an encrypted data A and an encrypted data B,

the cipher processing method comprising;

inputting the data A to be encrypted to hold in the register A, holding the data A to be input to the first operating step in the register A, outputting the data A to the first operating step, and outputting the encrypted data A from the register A after repeatedly operating the first operating step;

inputting the data B to be encrypted to hold in the register B, holding the data B to be input to the first operating step in the register B, outputting the data B to the first operating step, and outputting the encrypted data B from the register B after repeatedly operating the first operating step;

provided in the first operating step, repeatedly holding the data C output from the second operating step in the register C and outputting the data C;

selecting one of the registers A, B and C, and outputting the data held in the register selected;

XORing the data selected by the selector C with the data A held in the register A by the XOR circuit A;

selecting a result XORed by the XOR circuit A and outputting the result to the register A to hold the result;

XORing the data output from the selector C with the data B held in the register B by the XOR circuit B;

selecting a result XORed by the XOR circuit B and outputting the result to the register B to hold the result;

wherein the first operating step includes the second operating step, the register C step and the selector C step;

the second operating step, the register C step and the selector C step form a first processing loop step inside of the first operating step for repeatedly performing a second data transformation by the second operating step; and

the XOR circuit A step, the XOR circuit B step, the selector A step, the selector B step, the register A step, and the register B step form a second processing loop for repeatedly performing the first data transformation by the first operating step;

wherein the second operating step inputs the data input from the selector C step, performs the second data transformation on the data and outputs the data to the register C to make the register C hold the data in the register C as data C;

wherein the selector C step alternately selects the data A held in the register A and the data B held in the register B to output to the second operating step for repeatedly performing the first data transformation by the first operating step alternately on the data A and the data B by initiating repeatedly performing the second data transformation by the second operating step in case of repeatedly operating the first operating step;

the selector C step selects the data C held in the register C to output to the second operating step for repeatedly performing the second data transformation by the second operating step in case of repeatedly performing the second data transformation by the second operating step; and

the selector C step selects the data C held in the register C to output to the XOR circuit A step and the XOR circuit B step for XORing the data in case of terminating the second data transformation by the second operating step being performed repeatedly, and

wherein the selector A step and the selector B step alternately select the result XORed by the XOR circuit A step and the result XORed by the XOR circuit B step and output the result to the registers A an d B to make the registers A and B alternately hold the result in case of terminating the second data transformation by the second operating step being performed repeatedly.