Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

• US 6,466,825 B1
• Filed: 08/10/2001
• Issued: 10/15/2002
• Est. Priority Date: 09/29/1998
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Wang, Yuanlong, Wei, Xiaofan, Baird, Brian R., Yu, Zong, Cohen, Earl T., Fu, Daniel
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): Bahta, Kidest
• Application Number:
  US09/927,717
• Time in Patent Office: 431 Days
• Field of Search: 700/5.9, 700/29, 710/100, 710/146, 710/29, 710/141.14, 710/113.1, 710/12, 711/110, 711/282, 711/200, 711/143, 711/119
• US Class Current: 700/5
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831

Abstract

A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both bus-based based and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.

Claims

1. A transaction bus for use with a multi-processor system operating on clock cycles of a clock and having a plurality of processor interfaces and at least one memory interface, the transaction bus comprising:

a bus structure configured to transfer transaction commands from individual ones of the interfaces and to allow all other ones of the interfaces to monitor the transaction commands; and

an arbiter configured to grant bus access to the interfaces for a transfer rate of one of the transaction commands per one of the clock cycles.

2. The transaction bus of claim 1 wherein the bus structure comprises a plurality of multiplexers configured to provide the bus access to an individual one of the interfaces in response to a control signal from the arbiter.

3. The transaction bus of claim 1 wherein the multi-processor system includes a transaction controller and the bus structure is configured to transfer the transaction commands from the interfaces to the transaction controller at the transfer rate.

4. The transaction bus of claim 3 wherein the transaction controller maintains transaction ordering.

5. The transaction bus of claim 3 wherein the transaction controller maintains cache coherency for the multi-processor system.

6. The transaction bus of claim 1 wherein the multi-processor system is symmetric.

7. The transaction bus of claim 1 wherein the arbiter is configured to use a rotating priority scheme to grant the bus access to the interfaces.

8. The transaction bus of claim 1 wherein the transaction commands include address data.

9. The transaction bus of claim 1 wherein one of the other ones of the interfaces initiates a speculative action in response to one of the transaction commands.

10. The transaction bus of claim 1 wherein the bus structure is segmented.

11. A method of operating a transaction bus for use with a multi-processor system operating on clock cycles of a clock and having a plurality of processor interfaces and at least one memory interface, the method comprising:

transferring transaction commands from individual ones of the interfaces over a bus structure;

allowing all other ones of the interfaces to monitor the transaction commands; and

granting bus access to the interfaces for a transfer rate of one of the transaction commands per one of the clock cycles.

12. The method of claim 11 further comprising using a plurality of multiplexers to provide the bus access to an individual one of the interfaces in response to a control signal from an arbiter.

13. The method of claim 11 wherein the multi-processor system includes a transaction controller and wherein transferring the transaction commands from the interfaces over the bus structure comprises transferring the transaction commands from the interfaces over the bus structure to the transaction controller at the transfer rate.

14. The method of claim 13 further comprising maintaining transaction ordering in the transaction controller.

15. The method of claim 13 further comprising maintaining cache coherency for the multi-processor system in the transaction controller.

16. The method of claim 11 wherein the multi-processor system is symmetric.

17. The method of claim 11 wherein granting the bus access to the interfaces comprises using a rotating priority scheme.

18. The method of claim 11 wherein the transaction commands include address data.

19. The method of claim 11 further comprising, in one of the other ones of the interfaces, initiating a speculative action in response to one of the transaction commands.

20. The method of claim 11 wherein the bus structure is segmented.