Simple and fast way for generating a harmonic signal

• US 6,466,903 B1
• Filed: 05/04/2000
• Issued: 10/15/2002
• Est. Priority Date: 05/04/2000
• Status: Expired due to Fees

• Current Assignee: AT&T Corporation (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Stylianou, Ioannis G
• Primary Examiner(s): Dorvil, Richemond
• Application Number:
  US09/564,437
• Time in Patent Office: 894 Days
• Field of Search: 704/207, 704/200, 704/201, 704/205, 704/209
• US Class Current: 704/207
• CPC Class Codes: G10L 13/02 Methods for producing synthetic speech; Speech synthesisers

Abstract

A fast and accurate method for generating a sampled version of the signal $h\left(t\right)=\sum _{k=1}^KA_k\cos \left(k{\omega }_ot+{\varphi }_k\right),$

is achieved by retrieving from memory a pre-computed phase delay value corresponding to φ_k for a given fundamental frequency, expressed in numbers of samples, for a running value of the index k, subtracting it from a sample time index, t, that is multiplied by the value of k, and employing the subtraction result, expressed in a modulus related to the fundamental frequency, to retrieve a pre-computed sample value of cosine cos(kω_ot) for the given fundamental frequency. The retrieved sample is multiplied by a retrieved coefficient A_k corresponding to the value of k and to the given fundamental frequency, and placed in an accumulator. The value of k is incremented, and the process for the sample value corresponding to the value of time sample t is repeated until the process completes for k=K.

Claims

1. A method executed in a computing apparatus for generating a time sample of a signal h(t) for sample time t, where $h$

(t)=∑

k=1K

Ak

cos

(k

 



ω

o

t+ϕ

k),

for a given fundamental frequency ω

_o, when the set A_k, k=1, 2, . . . K is given for said fundamental frequency, and the set τ

_k, k=1, 2, . . . K is given for said fundamental frequency, where τ

_k is related to φ

_k through said fundamental frequency, comprising the steps of;

setting index k to 1;

retrieving from memory the value of τ

_k corresponding to index k;

developing a number corresponding to [tk−

τ

_k]_modT where T is related to said fundamental frequency;

employing said number to develop a cosine sample at said fundamental frequency;

multiplying said cosine sample by a coefficient A_k corresponding to index k that is retrieved from memory;

accumulating results of said step of multiplying;

while k is less than K−

1, incrementing k and returning to said step of retrieving;

when k is equal to K, assigning results of said accumulating to said h(t).

2. The method of claim 1 where said step of developing a cosine sample from said number comprises retrieving a pre-computed cosine sample from memory.

3. The method of claim 1 further comprising a step of selecting a fundamental frequency.

4. The method of claim 3 where said step of selecting a fundamental frequency is effected by focusing said retrieving of τ

_k from memory, retrieving of A_k from memory and retrieving sad cosine sample from memory on sections of memory that contain information related to said fundamental frequency.

5. The method of claim 1 further comprising incrementing the value of t and repeating said steps of setting index k to 1 through assigning results of said accumulating to said h(t).

6. The method of claim 1 further comprising computing, and storing in memory, values of τ

_k from given values of φ

_k, where τ

_k=−

φ

(kω

_o)/kω

_o, rounded to the nearest integer.

7. Apparatus comprising:

a controller for developing an index signal t and an index signal k;

a memory for storing coefficients A_k for a selected fundamental frequency ω

_o, responsive to said index signal k;

a memory for storing delay values τ

_k for said fundamental frequency ω

_o, responsive to said index signal k;

a computing circuit responsive to said index signal t, said index signal k, and to output signal of said memory for storing delay values;

a memory for storing sample values of cosine for said selected fundamental frequency;

a multiplier responsive to output signal of said memory for storing coefficients and to output signal of said memory for storing sample values of cosine; and

an accumulator responsive to said multiplier.

8. The apparatus of claim 7 where said computing circuit develops a number corresponding to [tk−

τ

_k]_modT where T is related to said fundamental frequency.

9. The apparatus of claim 7 where said computing circuit comprises a multiplier responsive to said index signal t and said index signal k, a subtractor responsive to said multiplier of said computing circuit and to said output signal of said memory for storing delay values, and a circuit for developing a remainder of the number developed by said subtractor, when that number is divided by T, where T is related to said fundamental frequency.

10. The apparatus of claim 7 wherein said controller develops a signal corresponding to said fundamental frequency, and said memory for storing coefficients A_k, said memory for storing delay values τ

_k, said computing circuit responsive, and said memory for storing sample values of cosine are all responsive to said signal corresponding to said fundamental frequency.