Processor reset generated via memory access interrupt
First Claim
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1. A method of resetting a processor, comprising:
- (a) generating a reset request for the processor;
(b) generating a memory access interrupt on the processor; and
(c) resetting the processor during handling of the memory access interrupt by the processor responsive to detection of the reset request.
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Abstract
An apparatus, program product, and method utilize a memory access interrupt to effect a reset of a processor in a multi-processor environment. Specifically, a source processor is permitted to initiate a reset of a target processor simply by generating both a reset request and a memory access interrupt for the target processor. The target processor is then specifically configured to detect the presence of a pending reset request during handing of the memory access interrupt, such that the target processor will perform a reset operation responsive to detection of such a request.
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Citations
33 Claims
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1. A method of resetting a processor, comprising:
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(a) generating a reset request for the processor;
(b) generating a memory access interrupt on the processor; and
(c) resetting the processor during handling of the memory access interrupt by the processor responsive to detection of the reset request. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of resetting a first processor among a plurality of processors in a multi-processor computer system, comprising:
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(a) detecting with a processor other than the first processor a likely lockup condition in the first processor while external interrupts on the first processor are disabled;
(b) generating with a processor other than the first processor a reset request for the first processor;
(c) generating with a processor other than the first processor a memory access interrupt on the first processor; and
(d) handling the memory access interrupt in the first processor, including detecting the reset request with the first processor and performing a reset on the first processor responsive thereto.
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18. An apparatus comprising first and second processors, wherein:
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(a) the second processor is configured to initiate a reset of the first processor by generating a reset request and a memory access interrupt for the first processor; and
(b) the first processor is configured to handle the memory access interrupt and to perform a reset responsive to detection of the reset request during handling of the memory access interrupt. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. An apparatus, comprising:
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(a) a memory defining a real address space with a plurality of real memory addresses;
(b) a first processor configured to access the memory using a virtual address space including a plurality of virtual memory addresses;
(c) an address translation table accessible by the first processor and including a plurality of entries, each entry configured to map a virtual memory address in the virtual address space to a real memory address in the real address space;
(d) a memory access interrupt handler configured to be executed by the first processor in response to an attempt by the first processor to access an unmapped virtual memory address in the address translation table, the memory access interrupt handler further configured to reset the first processor responsive to a pending reset request; and
(e) a second processor coupled to the first processor, the second processor configured to initiate a reset of the first processor by generating a reset request and invalidating at least one entry in the address translation table. - View Dependent Claims (31)
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32. A program product, comprising:
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(a) first and second programs respectively configured to execute on first and second processors, the second program configured to initiate a reset of the first processor by generating a reset request and a memory access interrupt for the first processor, and the first program configured to handle the memory access interrupt and to perform a reset responsive to detection of the reset request during handling of the memory access interrupt; and
(b) a signal bearing medium bearing the first and second programs. - View Dependent Claims (33)
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Specification