Configurable processor system unit
First Claim
Patent Images
1. A configurable processor system unit comprising:
- a processor;
at least one region of random access memory (RAM) based dynamically configurable volatile programmable logic; and
a bus coupling the processor and the at least one region of programmable logic;
wherein the processor, the programmable logic, and the bus are implemented on a single integrated circuit.
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Accused Products
Abstract
The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
336 Citations
109 Claims
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1. A configurable processor system unit comprising:
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a processor;
at least one region of random access memory (RAM) based dynamically configurable volatile programmable logic; and
a bus coupling the processor and the at least one region of programmable logic;
wherein the processor, the programmable logic, and the bus are implemented on a single integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
an array of banks, each bank including a plurality of tiles, wherein each tile may be programmed to perform a function.
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36. The configurable processor system unit of claim 35, wherein the at least one region of programmable logic further comprises:
a plurality of breaker tiles arranged between the banks, the breaker tiles for leading signals into the tiles.
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37. The configurable processor system unit of claim 36, wherein the breaker tiles comprise:
a vertical breaker and a horizontal breaker associated with each bank, such that each bank is surrounded by all four sides by breaker tiles.
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38. The configurable processor system unit of claim 37, wherein the breaker tiles further comprise a corner breaker tile.
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39. The configurable processor system unit of claim 36, wherein the break tiles include system level circuitry and receive and distribute data signals, address signals, control signals to the bank.
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40. The configurable processor system unit of claim 36, wherein the at least one region of programmable logic comprises short lines that connect adjacent tiles within a bank.
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41. The configurable processor system unit of claim 40, wherein the at least one region of programmable logic further comprises long lines extending across multiple tiles in a bank.
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42. The configurable processor system unit of claim 41, wherein the breaker tiles comprise programmable connections between the long lines between adjacent banks.
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43. The configurable processor system unit of claim 36, wherein the bus is distributed such that a copy of the bus is distributed to each bank across the breaker tiles.
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44. The configurable processor system unit of claim 43, wherein:
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an address bus is distributed down the column of the horizontal breakers;
a write data bus is distributed down the column of the vertical breakers;
a read data bus is distributed up the column of vertical breakers.
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45. The configurable processor system unit of claim 44, wherein additional global signals are distributed across the programmable logic using the breaker tiles.
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46. The configurable processor system unit of claim 35, wherein a bank comprises an 8 tile by 8 tile row by column array of logic block tiles.
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47. The configurable processor system unit of claim 36, further comprising additional breaker tiles at an edge of the region of programmable logic, the additional breaker tiles designed to accommodate input/output (I/O) pads for the region of programmable logic.
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48. The configurable processor system unit of claim 35, wherein the tile comprises:
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an address decoder;
a data path element; and
a block of programmable logic and interconnect (PLAI).
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49. The configurable processor system unit of claim 48, wherein the address decoder is for generating a match signal.
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50. The configurable processor system unit of claim 48, wherein the data path element is for driving signals into and out of the PLAI.
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51. The configurable processor system unit of claim 48, wherein the PLAI comprises:
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a programmable logic block for implementing a function;
a horizontal input mux array for driving and selecting one or more signals running through the tile;
a vertical input mux array for driving and selecting one or more signals running through the tile;
a zip switch box for performing switching functions among a plurality of available signals.
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52. The configurable processor system unit of claim 35, further comprising a data path chain for connecting signals to individual tiles within the region of programmable logic.
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53. The configurable processor system unit of claim 52, wherein a single active signal from a single tile injected into the data path chain, such that one tile drives the signal.
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54. The configurable processor system unit of claim 36, wherein a multi-source distributed signal is driven to the region of programmable logic by an array structure that allows a signal source to drive the array structure at any point, and provides a logical OR function of all sources to the array at any point of the array.
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55. The configurable processor system unit of claim 54, wherein the multi-source distributed signal is a wait control signal.
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56. The configurable processor system unit of claim 35, wherein the region of programmable logic further includes a configuration memory space used to partially or fully configure or reconfigure the region of programmable logic.
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57. The configurable processor system unit of claim 56, wherein the processor can address the configuration memory space as part of the system address space.
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58. The configurable processor system unit of claim 56, wherein a bank of the region of programmable logic may be disconnected from other banks and may be dynamically reconfigured without affecting operations of circuits programmed into other banks.
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59. The configurable processor system unit of claim 1, wherein the bus is a multi-master shared bus, and the processor includes a hold signal to interact with the multi-master shared bus.
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60. The configurable processor system unit of claim 1, wherein specific address spaces addressed by the processor are remapped, such that the processor addresses a single larger address space, that may include areas of the region of programmable logic.
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61. The configurable processor system unit of claim 1, further comprising a bypass bus coupling the processor to a memory to reduce memory latency.
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62. The configurable processor system unit of claim 61, wherein the processor arbitrates for the bus when using the bypass bus.
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63. The configurable processor system unit of claim 1, further comprising an external memory interface unit providing a connection between the processor and an external memory, the connection bypassing the bus.
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64. The configurable processor system unit of claim 1, wherein the bus comprises a plurality of segments coupling an arbiter, at least one master device, and the programmable logic together.
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65. The configurable processor system unit of claim 64, wherein an arbitration segment of the bus couples the arbiter and the master device for arbitration requests and response signals.
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66. The configurable processor system unit of claim 64, wherein a master write segment couples signals from the master device to a bus pipe, and a master read segment couples signals from the bus pipe to the master device.
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67. The configurable processor system unit of claim 64, wherein the master write segment collects a plurality of master signals into a consolidated bus.
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68. The configurable processor system unit of claim 67, wherein the master write segment comprises multiplexors for collecting individual master signals into the consolidated bus.
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69. The configurable processor system unit of claim 64, wherein a slave write segment couples signals from the bus pipe to the programmable logic, and a slave read segment couples the signals from the programmable logic to the bus pipe.
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70. The configurable processor system unit of claim 69, wherein the slave write segment couples the signals to selectors and pipe registers distributed throughout the programmable logic.
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71. The configurable processor system unit of claim 70, wherein a socket interface write segment carries signals from the selectors and the pipe registers to the slaves within the programmable logic.
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72. The configurable processor system unit of claim 71, wherein a socket interface read segment collects signals from the slaves to return pipe registers.
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73. The configurable processor system unit of claim 72, wherein the signals collected from the slaves are routed through a general-purpose configurable logic of the programmable logic.
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74. The configurable processor system unit of claim 72, wherein the socket interface read segment further comprises logical OR gates for collecting the signals into consolidated bus signals at the return pipe registers.
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75. The configurable processor system unit of claim 69, wherein a slave read segment couples signals from the programmable logic to the bus pipe.
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76. A system on an integrated circuit comprising:
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a processor;
an internal system bus; and
a repetitive, block based, dynamically configurable programmable logic coupled to the processor by the internal system bus. - View Dependent Claims (77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
an array of banks, each bank including a plurality of tiles, wherein each tile may be programmed to perform a function. a plurality of breaker tiles arranged between the banks, the breaker tiles for leading signals into the tiles, wherein the breaker tiles comprise a vertical breaker and a horizontal breaker associated with each bank, such that each bank is surrounded by all four sides by breaker tiles.
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82. The system of claim 81, wherein the logic banks include an embedded extension of the bus.
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83. The system of claim 82, wherein:
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an address bus is distributed down the column of the horizontal breakers;
a write data bus is distributed down the column of the vertical breakers;
a read data bus is distributed up the column of vertical breakers.
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84. The system of claim 76, wherein the programmable logic comprises:
an array of banks, each bank including a plurality of tiles, wherein each tile may be programmed to perform a function.
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85. The system of claim 84, wherein programmable logic further comprises:
a plurality of breaker tiles arranged between the banks, the breaker tiles for leading signals into the tiles.
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86. The system of claim 85, wherein additional global signals are distributed across the programmable logic using the breaker tiles.
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87. The system of claim 86, wherein a bank comprises an 8 tile by 8 tile row by column array of logic block tiles.
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88. A system comprising:
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a means for high performance processing;
a means for coupling signals between components of the system; and
a means for configuring customized gate arrays in a RAM-based logic circuit;
wherein the means for processing, the means for coupling and the means for configuring are implemented on a single substrate.
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89. A configurable processor system unit comprising:
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a processor;
at least one region of programmable logic dynamically configurable by the processor; and
a bus coupling the processor and the programmable logic;
wherein the processor, the programmable logic and the bus are implemented on a single integrated circuit. - View Dependent Claims (90)
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91. A configurable system-on-a-chip comprising:
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a processor;
at least one region of dynamically reconfigurable programmable logic that may be a bus master; and
a system bus coupling the processor and the programmable logic; and
a bus arbitration logic to arbitrate bus access between multiple masters. - View Dependent Claims (92, 93)
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94. A configurable system-on-a-chip comprising:
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a processor;
at least one region of programmable logic, the programmable logic further providing input/output (I/O) to the system-on-a-chip; and
a bus coupling the processor and the programmable logic. - View Dependent Claims (95, 96, 97, 98, 99, 100)
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101. A configurable system-on-a-chip comprising:
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a processor;
a dynamically configurable programmable logic that may be reconfigured during run-time; and
a bus coupling the processor and the programmable logic. - View Dependent Claims (102, 103, 104, 105, 106, 107, 108, 109)
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Specification