Shared memory apparatus and method for multiprocessor systems
First Claim
1. An adapter for coupling a processor system to a shared memory unit over a data link, the processor system having a data bus for access to a local memory and a standard expansion bus coupled to the data bus, the shared memory unit having at least one bank of shared memory, the adapter comprising:
- an on-board bus coupling the adapter to the expansion bus of the processor system;
an input/output port coupling the adapter to the shared memory unit via the data link;
an interface coupled to the on-board bus for monitoring processor memory accesses on the data bus and placing a memory access completion acknowledgement indication on the expansion bus;
a transaction unit coupled to the interface for detecting when a monitored processor memory access is a processor memory access operation to a memory address value within a range of addresses corresponding to the shared memory;
a link manager coupled to the transaction unit for translating the monitored processor memory access operation into a shared memory access request; and
an input/output port physical interface for outputting the shared memory access request to the input/output port and, in turn, to the shared memory unit;
whereby it is transparent to the processor system whether the memory access operation is addressed to the local memory or to the shared memory.
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Abstract
A memory alias adapter, coupled to a processors memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor'"'"'s memory access on the memory bus. As a result, it is transparent to the processor whether its memory access is to the local memory or to the shared memory,
53 Citations
15 Claims
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1. An adapter for coupling a processor system to a shared memory unit over a data link, the processor system having a data bus for access to a local memory and a standard expansion bus coupled to the data bus, the shared memory unit having at least one bank of shared memory, the adapter comprising:
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an on-board bus coupling the adapter to the expansion bus of the processor system;
an input/output port coupling the adapter to the shared memory unit via the data link;
an interface coupled to the on-board bus for monitoring processor memory accesses on the data bus and placing a memory access completion acknowledgement indication on the expansion bus;
a transaction unit coupled to the interface for detecting when a monitored processor memory access is a processor memory access operation to a memory address value within a range of addresses corresponding to the shared memory;
a link manager coupled to the transaction unit for translating the monitored processor memory access operation into a shared memory access request; and
an input/output port physical interface for outputting the shared memory access request to the input/output port and, in turn, to the shared memory unit;
whereby it is transparent to the processor system whether the memory access operation is addressed to the local memory or to the shared memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification
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- Resources
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Current AssigneeIII Holdings 4, LLC
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Original AssigneeTimes N Systems
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InventorsWest, Lynn Parker, Scardamalia, Theodore G.
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Primary Examiner(s)Thai, Xuan M.
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Application NumberUS09/859,193Publication NumberTime in Patent Office518 DaysField of Search710/62, 710/63, 710/72, 710/74, 710/305, 710/100, 710/300, 710/316, 710/317, 710/65, 710/23, 710/26, 711/100, 711/1, 711/147, 711/148, 711/154, 711/202US Class Current710/305CPC Class CodesG06F 13/1663 Access to shared memory
