Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors

• US 6,467,012 B1
• Filed: 07/08/1999
• Issued: 10/15/2002
• Est. Priority Date: 07/08/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Alvarez, Manuel, Gruger, Jeffrey Holland, Deshpande, Sanjay Raghunath, Geiger, Peter Dau
• Primary Examiner(s): Wong, Peter
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US09/350,031
• Time in Patent Office: 1,195 Days
• Field of Search: 710/316, 710/317, 711/141, 709/213
• US Class Current: 710/316
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration

Abstract

A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller'"'"'s master device buses. The memory subsystems contain a memory controller and a fixed delay pipe from the address port to the memory controller so that the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.

Claims

1. A data processing system comprising:

a plurality of master devices;

a plurality of nodes, wherein a subset of one or more master devices are organized into a node;

an address switch;

a plurality of memory subsystems;

each one of said plurality of nodes being controlled by a separate node controller;

each node controller being coupled to said address switch utilizing a pair of address buses, said pair of address buses carrying only addresses;

each node controller also being connected directly to each one of said plurality of memory subsystems utilizing a separate data bus, said data bus carrying only data; and

said address switch being coupled to each one of said plurality of memory subsystems utilizing a separate address bus, said address bus carrying only addresses.

2. The data processing system of claim 1 wherein a master device is a processor, or an input/output agent, or a coherent memory adapter.

3. The data processing system of claim 1 further comprising:

a plurality of bidirectional master device buses, wherein a master device bus connects one or more master devices within a node to a port of the node controller.

4. The data processing system of claim 1 wherein each node controller comprises:

a plurality of master device ports, wherein each master device port connects to a master device bus;

a pair of address switch ports, each one of said pair of address switch ports connecting to one of a pair of unidirectional address switch buses, said pair of unidirectional address switch buses also being connected to said address switch, wherein one of the pair of address switch buses conveys an address from the node controller to the address switch and the other one of the pair of address switch buses conveys an address from the address switch to the node controller; and

a plurality of memory subsystem ports, each one of said plurality of memory subsystem ports connecting to a different, single bidirectional memory subsystem bus, said bidirectional memory subsystem bus also being connected to a different one of said plurality of memory subsystems, wherein a memory subsystem bus conveys data between the node controller and one of the memory subsystems.

5. The data processing system of claim 1 wherein each node controller comprises:

a data controller; and

an address controller.

6. The data processing system of claim 5 wherein said data controller comprises:

a plurality of master device data ports, wherein each master device data port connects to a data portion of a master device bus; and

a plurality of memory subsystem ports, each one of said plurality of memory subsystem ports connecting to a different, single bidirectional memory subsystem bus, said bidirectional memory subsystem bus also being connected to a different one of said plurality of memory subsystems, wherein a memory subsystem bus conveys data between the data controller and the memory subsystem that is connected to the memory subsystem bus.

7. The data processing system of claim 5 wherein said address controller comprises:

a plurality of master device address ports, wherein each master device address port connects to an address portion of a master device bus; and

a pair of address switch ports, each one of said pair of address switch ports connecting to one of a pair of unidirectional address switch buses, said pair of unidirectional address switch buses also being connected to said address switch, wherein one of the pair of address switch buses conveys an address from the address controller to the address switch, and the other one of the pair of address switch buses conveys an address from the address switch to the address controller.

8. The data processing system of claim 5, further comprising:

said data controller and said address controller being separate physical devices.

9. The data processing system of claim 1 wherein the node controller receives commands from a master device.

10. The data processing system of claim 1 wherein a command comprises one or more elements in a group consisting of the following elements:

a transaction tag;

a transaction type;

a target address; and

a source address.

11. The data processing system of claim 10 wherein a transaction type indicates a variety of transactions that may be performed within the data processing system read request or a write request from a memory subsystem.

12. The data processing system of claim 1 wherein the node controller communicates with a master device as another master device or as a slave device.

13. The data processing system of claim 1 wherein the node controller queues commands received from the master devices.

14. The data processing system of claim 1 wherein the node controller has a deterministic delay between latching a command broadcast by the address switch and presenting the command to the master devices on the node controller'"'"'s master devices buses.

15. The data processing system of claim 1 wherein the node controller comprises a cache-to-cache buffer for queueing data for transferring data from a master device connected to the node controller to another master device connected to the node controller.

16. The data processing system of claim 1 wherein the data throughput of a port within the node controller is independent of the total number of ports in the data processing system.

17. The data processing system of claim 1 wherein the address switch further comprises:

a plurality of pairs of node address ports, wherein each pair of node address ports connects to a node controller via a pair of unidirectional address buses, wherein one of the pair of address buses conveys an address from the node controller to the address switch and the other one of the pair of address buses conveys an address from the address switch to the node controller; and

a plurality of memory subsystem address ports, wherein each memory subsystem address port connects to a memory subsystem via a unidirectional address bus for conveying an address from the address switch to the memory subsystem.

18. The data processing system of claim 1 wherein a memory subsystem further comprises:

a plurality of node data ports, wherein each node data port connects to a different node controller via a bidirectional data bus, wherein the bidirectional data bus conveys data between the node controller and the memory subsystem; and

an address port, wherein the address port connects the memory subsystem to the address switch via a unidirectional address bus for receiving an address from the address switch.

19. The data processing system of claim 18 wherein the memory subsystem further comprises:

a memory controller; and

a fixed delay pipe from the address port to the memory controller, wherein the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller.

20. The data processing system of claim 1 wherein buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a plurality of bus protocols.

21. The data processing system of claim 1 wherein the plurality of master devices comprise a plurality of processors.

22. The data processing system of claim 21 wherein the plurality of processors comprise a plurality of caches.

23. The data processing system of claim 22 wherein the data processing system employs a bus-based snooping protocol.

24. The data processing system of claim 23 wherein the data processing system is a symmetric multiprocessor (SMP) system.

25. The data processing system of claim 1, further comprising:

each node controller having a deterministic delay between latching a command broadcast by the address switch and presenting the command to the master devices on the node controller'"'"'s master devices buses, each one of the master devices included in each one of the plurality of nodes being presented with the command at a same time.

26. The data processing system of claim 1, further comprising:

each node controller having a deterministic delay between latching a command broadcast by the address switch and presenting the command to the master devices on the node controller'"'"'s master devices buses, each one of the master devices included in each one of the plurality of nodes being presented with the command at a same time;

each one of said plurality of memory subsystems including a memory controller;

each one of said plurality of memory subsystems including a fixed delay pipe from the address port to the memory controller, wherein the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller; and

said fixed delay pipe being adjusted so that each one of the master devices included in each one of the plurality of nodes is presented with a command at a same time one of said plurality of memory subsystems is presented with said command.

27. The data processing system of claim 1, further comprising:

said address switch being coupled to each one of said plurality of memory subsystems utilizing a separate, single address bus.

28. The data processing system of claim 1, further comprising:

each node controller also being connected directly to each one of said plurality of memory subsystems utilizing a separate, single data bus.