Apparatus, method and system for using cache memory as fail-over memory
First Claim
1. A computer system providing automatic fail-over of information stored in memory locations having an undesired number of errors to cache-lines of a cache memory during operation of the computer system, the computer system comprising:
- a central processing unit;
a memory controller connected to the central processing unit;
a main memory comprising a plurality of memory locations having information stored therein, wherein the main memory is connected to the memory controller;
memory error detection and correction logic for determining and correcting errors in the information stored in the plurality of memory locations during access of the main memory;
a first cache memory comprising a plurality of first cache-lines and a plurality of first cache tag registers, each of the first cache tag registers being associated with a respective one of the first cache-lines, each of the first cache tag registers comprising an address portion, a status portion and a fail-over memory portion, wherein information is stored in at least one of the first cache-lines of the first cache memory during access of the main memory; and
fail-over logic connected to the memory error detection and correction logic and first cache memory, wherein the fail-over logic sets the fail-over memory portion of the first cache tag register associated with the first cache-line storing information from at least one of the plurality of memory locations that has an undesired number of errors detected by the memory error detection and correction logic, and so long as the fail-over memory portion is set, the respective first cache-line cannot be written over during subsequent accesses of the main memory.
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Accused Products
Abstract
A computer system having a main memory and a cache memory, the computer system uses portions of the cache memory to store information from defective main memory locations until the main memory can be repaired. The address space of the main memory is always maintained by substituting cache-lines of cache memory for the defective main memory locations. A fail-over memory status bit in the cache memory controller indicates when a cache line of the cache memory contains fail-over information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm. When the fail-over status bit is set, the contents of the fail-over memory location(s) remains in the cache-line and all memory reads and writes are directed to only that cache-line of the cache memory and not the main memory for the fail-over memory location(s). Also no write-back of the fail-over memory location(s) from cache memory to the main memory is required nor desired until the main memory location is repaired or replaced. Indicator lights may be used to represent the different activities of the main and cache memories at detection of the defective memory location, during and after fail-over from the main memory location to the cache-line, and transfer back to the main memory once repaired. A plurality of cache memories may migrate fail-over information therebetween.
108 Citations
39 Claims
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1. A computer system providing automatic fail-over of information stored in memory locations having an undesired number of errors to cache-lines of a cache memory during operation of the computer system, the computer system comprising:
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a central processing unit;
a memory controller connected to the central processing unit;
a main memory comprising a plurality of memory locations having information stored therein, wherein the main memory is connected to the memory controller;
memory error detection and correction logic for determining and correcting errors in the information stored in the plurality of memory locations during access of the main memory;
a first cache memory comprising a plurality of first cache-lines and a plurality of first cache tag registers, each of the first cache tag registers being associated with a respective one of the first cache-lines, each of the first cache tag registers comprising an address portion, a status portion and a fail-over memory portion, wherein information is stored in at least one of the first cache-lines of the first cache memory during access of the main memory; and
fail-over logic connected to the memory error detection and correction logic and first cache memory, wherein the fail-over logic sets the fail-over memory portion of the first cache tag register associated with the first cache-line storing information from at least one of the plurality of memory locations that has an undesired number of errors detected by the memory error detection and correction logic, and so long as the fail-over memory portion is set, the respective first cache-line cannot be written over during subsequent accesses of the main memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 32, 33, 34)
a plurality of second cache-lines and a plurality of first cache tag registers, each of the second cache tag registers being associated with a respective one of the second cache-lines, each of the second cache tag registers comprising an address portion, a status portion and a fail-over memory portion, wherein information is stored in at least one of the second cache-lines of the first cache memory during access of the first cache memory; and
the fail-over logic connected to the memory error detection and correction logic and second cache memory, wherein the fail-over logic sets the fail-over memory portion of the second cache tag register associated with the second cache-line storing information from at least one of the first cache-lines that has an undesired number of errors detected by the memory error detection and correction logic, and so long as the fail-over memory portion is set, the respective second cache-line cannot be written over during subsequent accesses of the first cache memory.
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21. The computer system of claim 1, further comprising a third cache memory associated with the central processing unit.
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22. The computer system of claim 1, further comprising a hard disk drive, a floppy disk drive, a CD ROM, a modem, a keyboard, a video controller and monitor, a mouse, a real time clock, a serial port, a parallel port, and a network interface card.
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32. The computer system of claim 1, further comprising a plurality of cache memories, each of said plurality of cache memories comprising a plurality of cache-lines and a plurality of cache tag registers, each of the plurality of cache tag registers being associated with a respective one of the plurality of cache-lines, each of the plurality of cache tag registers comprising an address portion, a status portion and a fail-over memory portion, wherein information is stored in at least one of the plurality of cache-lines of a one of the plurality of cache memories during access of the main memory, wherein said fail-over logic sets the fail-over memory portion of the cache tag register associated with the at least one of the plurality of cache lines of the one of the plurality of cache memories.
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33. The computer system of claim 32, further comprising logic for migrating information stored in at least one cache-line of the one cache memory to a cache line of another one of the plurality of cache memories and setting the fail-over memory portion of the cache tag register associated with the another one of the plurality of cache memories.
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34. The computer system of claim 33, wherein the fail-over memory portion of the cache tag register of the at least one cache-line is reset when the fail-over memory portion of the cache tag register of the another one of the plurality of cache memories is set.
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23. A core logic chipset, comprising:
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a host bus interface adapted for connection to a central processing unit;
a memory controller adapted for connection to a main memory comprising a plurality of memory locations having information stored therein;
memory error detection and correction logic for determining and correcting errors in the information stored in the plurality of memory locations during access of the main memory;
a cache memory comprising a plurality of cache-lines and a plurality of cache tag registers, each of the cache tag registers being associated with a respective one of the cache-lines, each of the cache tag registers comprising an address portion, a status portion and a fail-over memory portion, wherein information is stored in at least one of the cache-lines of the cache memory during access of the main memory; and
fail-over logic connected to the memory error detection and correction logic and cache memory, wherein the fail-over logic sets the fail-over memory portion of the cache tag register associated with the cache-line storing information from at least one of the plurality of memory locations that has an undesired number of errors detected by the memory error detection and correction logic, and so long as the fail-over memory portion is set, the respective cache-line cannot be written over during subsequent accesses of the main memory.
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24. A method in a computer system for providing automatic fail-over of information stored in memory locations having an undesired number of errors to cache-lines of a cache memory during operation of the computer system, the method comprising the steps of:
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detecting an error in information read from a memory location in a main memory;
determining if the memory location has an undesired number of errors, wherein if the memory location has the undesired number of errors, then writing the information to a first cache-line of a first cache memory, and setting a first fail-over status bit associated with the first cache-line so as to prevent the first cache-line from being written over during subsequent cache-line replacements, and if the memory location does not have the undesired number of errors, then writing the information to the first cache-line of the first cache memory without setting the first fail-over status bit. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 35, 36, 37, 38, 39)
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Specification