Captured synchronous DRAM fails in a working environment

• US 6,467,053 B1
• Filed: 06/28/1999
• Issued: 10/15/2002
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Connolly, Brian J., Mallabar, James R., Hazelzet, Bruce G., Kellogg, Mark W., Grundon, Steven A.
• Primary Examiner(s): BADERMAN, SCOTT T
• Application Number:
  US09/340,804
• Time in Patent Office: 1,205 Days
• Field of Search: 714/39, 714/42, 714/30, 710/301, 710/302, 711/5
• US Class Current: 714/39
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system'"'"'s memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.

Claims

1. A synchronous memory testing system comprising:

means for comparing a first memory module against a second memory module under actual working conditions in a computing device, wherein said first memory module is known to be working as expected and said second memory module is of unknown quality;

means for re-driving signals from said computing device to said means for comparing; and

means for providing information on failure of said second memory module.

2. A synchronous memory testing system as recited in claim 1, wherein said information on failures includes data, address and control signal patterns, and a location of said failure in said second memory module.

3. A synchronous memory testing system as recited in claim 1, wherein said first and second memory modules are of a type of high speed synchronous Dynamnic Random Access Memories (DRAMs) including Dual In-line Memory Modules (DIMMs).

4. A synchronous memory testing system as recited in claim 1, wherein said first and second memory modules operate as high speed synchronous Dynamic Random Access Memories (DRAMs) at memory bus speeds of 66 Mhz or higher.

5. A synchronous memory testing system comprising:

a computing device having memory; and

a test assembly connected to a memory module socket in a memory bank of said computing device, performing memory diagnostics and error reporting, wherein said test assembly re-drives clock signals.

6. A synchronous memory testing system recited in claim 5, wherein said computing device is a server, workstation, personal computer (PC) or laptop computer.

7. A synchronous memory testing system as recited in claim 5, wherein said test assembly captures failures and logs information about said failures in real time, generating error signals to permit probing.

8. A synchronous memory testing system as recited in claim 5, wherein said test assembly re-drives data signals to minimize system loading.

9. A synchronous memory testing system as recited in claim 5, wherein said test assembly is implemented in a first and second section to permit form/fit into limited space applications and a reduction of mechanical stress, said first section performing as an adapter card connected to said computing device via a memory module socket, and said second section performing as a diagnostic card connected to said adapter card via at least one high frequency ribbon cable.

10. A synchronous memory testing system as recited in claim 9, wherein said diagnostic card is provided with an independent and separate power supply, permitting said diagnostic card to be fully powered and operational prior to powering up the computing device and associated memory modules, enabling said diagnostic card to detect a first memory fail without delay.

11. A synchronous memory testing system as recited in claim 9, further comprising a logic analyzer connected to said diagnostic card, wherein said logic analyzer displays information on failure of memory modules.

12. A synchronous module adapter card comprising:

a system interface permitting connection to a memory module socket in a memory bank of a computing device;

a test card socket for a first memory module;

a system card socket for a second memory module, wherein said second memory module is of a similar type as said first memory module;

means for connecting said adapter card to a diagnostic card, enabling data, control and clock signals to be sent from said adapter card to said diagnostic card;

means for re-driving control, data and clock signals emanating from said computing device and said test card socket and said system card socket, wherein said signals are sent to said diagnostic card; and

means for probing said adapter card for high and low speed signals.

13. A synchronous module adapter card as recited in claim 12, wherein means for re-driving signals comprises an adjustable clock permitting timing optimization and characterization.

14. A synchronous module adapter card as recited in claim 13, wherein said adjustable clock allows said adapter card to be taller, thereby accommodating additional wire lengths, enabling use with more memory module form factors without interfering with other system components.

15. A synchronous module adapter card as recited in claim 14, wherein said adjustable clock allows multiple memory modules without impacting system loading.

16. A synchronous module adapter card as recited in claim 12, wherein means for re-driving timing signals comprises a logic re-drive or re-clocking circuit.

17. A synchronous module adapter card as recited in claim 16, wherein said logic re-drive allows multiple memory modules without impacting system loading.

18. A synchronous module diagnostic card comprising:

means for receiving re-driven control and timing signals and data bits from an adapter card;

control logic comparing a system memory module and a test memory module, wherein said memory modules are connected to said adapter card and data bits are passed to said diagnostic card from said adapter card via said receiving means; and

means for analyzing and displaying failure information.

19. A synchronous module diagnostic card as recited in claim 18, wherein said means for analyzing and displaying failure information is switch programmable to display only the address in use by said test memory module.

20. A synchronous module diagnostic card as recited in claim 18, wherein said control logic is implemented using field programmable gate arrays (FPGAs) and erasable programmable read only memory (EPROMS), enabling modification of operating characteristics of onboard logic.