Segmented compaction with pruning and critical fault elimination
First Claim
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1. A method of generating a vector set, said vector set being used for testing sequential circuits, said method comprising:
- a) selecting a plurality of fault models;
b) identifying a fault list each for each of said plurality of fault models;
c) identifying a vector set each for each of said fault lists;
d) selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit;
e) compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and
f) creating a vector set by combining all vector sets compacted in step e.
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Abstract
A method of generating a vector set, said vector set being used for testing sequential circuits. The method comprises selecting a plurality of fault models, identifying a fault list each for each of said plurality of fault models, identifying a vector set each for each of said fault lists, selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit, compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and creating a vector set by combining all vector sets compacted. A system and a computer program product for testing circuits with a compacted vector set where the compacted vector set is created by dropping faults based on a tolerance limit.
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Citations
26 Claims
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1. A method of generating a vector set, said vector set being used for testing sequential circuits, said method comprising:
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a) selecting a plurality of fault models;
b) identifying a fault list each for each of said plurality of fault models;
c) identifying a vector set each for each of said fault lists;
d) selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit;
e) compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and
f) creating a vector set by combining all vector sets compacted in step e. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of generating a test vector set, said test vector set being used for testing a sequential circuit, said method comprising:
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a) specifying a fault coverage;
b) identifying a list of faults that are covered and a list of faults that are not covered;
c) compacting said vector set so that fault coverage after compaction is at least as large as fault coverage specified in step a, wherein during each iteration of compaction faults may be exchanged between said list of faults that are covered and said list of faults that are not covered.
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11. A system for testing VLSI circuits comprising a test generator, the test generator further comprising:
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a fault model selector for selecting a plurality of fault models;
a fault list identifier for identifying a fault list each for each of said plurality of fault models;
a vector set identifier for identifying a vector set each for each of said fault lists;
a tolerance limit selector for selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit;
a dropped-fault compactor for compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and
a vector set creator for combining all compacted vector sets. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A computer program product including a computer-readable media comprising computer code that enables a VLSI tester to test VLSI circuits, said computer code comprising:
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a fault model selector code for enabling a computer to select a plurality of fault models;
a fault list identifier code for enabling a computer to identify a fault list each for each of said plurality of fault models;
a vector set identifier code for enabling a computer to identify a vector set each for each of said fault lists;
a tolerance limit code selector for enabling a computer to select a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit;
a dropped-fault compactor code for enabling a computer to compact each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and
a vector set creator code for enabling a computer to combine all compacted vector sets. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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Specification
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Current AssigneeNEC Corporation
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Original AssigneeNEC USA Inc (NEC Corporation)
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InventorsDoreswamy, Kiran B., Chakradhar, Srimat T., Bommu, Surendra K.
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Primary Examiner(s)Chung, Phung M.
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Application NumberUS09/389,590Time in Patent Office1,138 DaysField of Search714/745, 714/738, 714/724US Class Current714/745CPC Class CodesG01R 31/318335 Test pattern compression or...G01R 31/318342 by preliminary fault modell...
