Digital data (multi-bit) storage with discrete analog memory cells

• US 6,467,062 B1
• Filed: 11/10/1998
• Issued: 10/15/2002
• Est. Priority Date: 12/10/1997
• Status: Expired due to Fees

• Current Assignee: Mordecai Barkan
• Original Assignee: Mordecai Barkan
• Inventors: Barkan, Mordecai
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/189,260
• Time in Patent Office: 1,435 Days
• Field of Search: 714/758, 714/752, 714/746, 360/64, 704/243
• US Class Current: 714/764
• CPC Class Codes: G11B 20/02 Analogue recording or reproducing
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence

Abstract

The present invention provides means to trade Ns (discrete analog storage media noise) with Np (process contributed noise), thus allowing for storage of more bits per memory cell than the amounts attainable by the common practice. The storage media may be of any analog type, such as FLASH, RAM (D or S), EPROMS of various types and even used with continuous analog data storage. By transforming the digital data prior to storage and store the transformed data is analog data, results an improvement in total S/N (Signal to Noise ratio), allowing for better utilization of discrete analog memory when compared with the implementation of conventional approaches. The better utilization is measured by the average amount of bits of data stored in each memory cell.

Claims

1. A storage memory for storing digital data comprising:

digital signal processing (DSP) means for transforming a digital data bit stream having a stored data component so as to provide an improved signal to noise ratio by altering levels associated with the digital data bit stream;

means for converting the transformed data to form analog data; and

discrete analog memory means for storing the analog data.

2. The storage memory of claim 1 wherein the digital data bit stream is organized into blocks of data having n words in each block with m bits in each word and wherein the transformed bit stream is formed into new blocks of n′

words in each new block with m′

bits in each new word.

3. The storage memory of claim 2 wherein n′

and m′

are equal to or greater than n and m, respectively.

4. The storage memory as in claim 3 further including error correction process (ECC) means for forming ECC coded digital data corresponding an original digital bit stream prior to a data transformation.

5. The storage memory as in claim 4 wherein the digital data stream has signal in components and noise in components, the storage memory further including means for coherently processing the stored analog data to form improved signal out components while forming noise out components which are modified to have some relatively high values, the ECC means providing data recovery with a relatively low error rate.

6. The storage memory as in claim 5 including means for concentrating the noise out components in a range close to zero to allow for decreasing quantization levels of the analog data before storage so that stored values associated with the analog data are denser for a given error rate.

7. The storage memory as in claim 6 including:

means for reading the analog data;

means for converting the analog data to form digitized analog data; and

means for restoring the digitized analog data to the digital data bit stream.

8. The storage memory as in claim 7 including DSP means for recovering the digital data bit stream from the analog data.

9. The storage memory as in claim 8 including:

means for grouping the ECC coded digital data into blocks of n words of m bits each;

means for converting the blocks of words formed by grouping the ECC coded digital data into new blocks of n′

words of m′

bits each; and

means for converting the ECC coded digital data to form the analog data to be stored in the discrete analog memory means.

10. The storage memory as in claim 9 including:

means for reading the stored analog data;

means for converting the read analog data to form digital data;

means for grouping the digital data into n′

words of m″

bits;

means for grouping the digital data of n′

words of m″

bits to form n words of m bits; and

means for recovering the digital data bit stream from the block of n words.

11. The storage memory as in claim 5 wherein the means for coherently processing the second signal includes means for performing at least one of an Inverse Fast Fourier Transform (IFFT) and a Fast Fourier Transform (FFT).

12. The storage memory as in claim 5 wherein the means for coherently processing the stored analog data to form the improved signal out components while forming noise out components which are modified to have some relatively high values include means for altering data power associated with the stored analog signal and means for altering power distribution associated with the noise out components.

13. In a storage memory for storing digital data, a method comprising:

transforming a digital data bit stream having a stored data component so as to provide an improved signal to noise ratio by altering levels associated with the digital data bit stream;

converting the transformed digital data to form analog data; and

storing the analog data.

14. The method as in claim 13 including organizing the digital data bit stream into blocks of data having n words in each block with m bits in each word, wherein the transformed bit stream is formed into new blocks of n′

words in each new block with m′

bits in each new word.

15. A memory device, the memory device being arranged to store digital data, the memory device comprising:

a first transformer, the first transformer being arranged to process the digital data for error detection and error correction, the first transformer further being arranged to transform the processed digital data to improve a signal to storage noise ratio associated with the digital data when the digital data is retrieved substantially by altering levels associated with the digital data bit stream;

a first converter, the first converter being arranged to convert the transformed digital data into at least one analog value; and

an analog storage mechanism, the analog storage mechanism being arranged to store the at least one analog value.

16. The memory device of claim 15, further including:

a reader, the reader being arranged to retrieve the at least one analog value from the analog storage mechanism;

a second converter, the second converter being arranged to convert the at least one analog value into a digital representation; and

a second transformer, the second transformer being arranged to transform the digital representation into the digital data.

17. The memory device of claim 16 wherein the second transformer is further arranged to check for errors associated with a transformation of the digital representation into the digital data and to correct for errors associated with the transformation of the digital representation into the digital data.

18. The memory device of claim 17 wherein the overall transformer is a digital signal processing mechanism.

19. The memory device of claim 15 wherein the analog storage mechanism is a discrete analog flash memory.

20. The memory device of claim 15 wherein the processed digital data is organized in blocks of n words each, each of the n words including m bits, and the transformed digital data is organized in blocks of n′

words each, each of the n′

words including m′

bits.

21. The memory device of claim 20 wherein the n words, the m bits, the n′

words, and the m′

bits are selected by the transformer to improve the signal to storage noise ratio while allowing a relatively low processing noise to be maintained.

22. The memory device of claim 20 wherein the first transformer is arranged to perform an inverse fast Fourier transform to transform the processed digital data, and the second transformer is arranged to perform a fast Fourier transform to transform the digital representation.

23. The storage memory as in claim 15 wherein the first transformer is arranged to transform the processed digital data to improve the signal to storage noise ratio associated with the digital data when the digital data is retrieved substantially by decreasing quantization levels associated with the digital data bit stream.