Method of placement and routing for an array device

• US 6,467,072 B1
• Filed: 05/06/1999
• Issued: 10/15/2002
• Est. Priority Date: 11/20/1998
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chang, Yung-Chung, Wang, Shu-Tzu, Yang, Chun-Chih
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/306,254
• Time in Patent Office: 1,258 Days
• Field of Search: 703/27, 716/5, 716/16, 716/18, 716/9, 716/2, 716/3, 716/12, 716/17, 716/14
• US Class Current: 716/119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The invention provides a method of placement and routing for an array device in an integrated circuit (IC). In the method, a schematic script file used to describe placement for the array device is created according to a netlist and an array structure specification. The schematic script file is loaded into an auto P&R tool. The auto P&R tool is executed for completely routing the array device. After routing, an RC extraction can be directly implemented. Thus, product development time is greatly shortened.

Claims

1. A method of placement and routing for an array device comprising the steps of:

providing a netlist and an array structure specification which describes an array device;

creating a schematic script file which describes placement for the array device according to the netlist and the array structure specification, wherein the schematic script file comprises a blockage where a routing program is instructed to build routing only for the array device;

loading the schematic script file into the routing program; and

executing the routing program for completely routing the array device.

2. The method of placement and routing for an array device as defined in claim 1, wherein the array device is a first in first out (FIFO) memory.

3. A method of placement and routing for an array device, wherein the array device has a plurality of elements, the method comprising the steps of:

providing a netlist and an array structure specification, wherein the netlist describes the relationship of electrical connections among the elements, and the array structure specification describes an arrangement of the elements;

creating a schematic script file which describes placement for the elements according to the netlist and the array structure specification, wherein the schematic script file comprises a blockage where a routing program is instructed to build routing only for the array device;

loading the schematic script into the routing program; and

executing the routing program for completely routing the elements.

4. The method of placement and routing for an array device as defined in claim 3, wherein the array device is a first in first out (FIFO) memory.

5. The method of placement and routing for an array device as defined in claim 3, wherein the elements comprises a plurality of memory units and control units.