Method and apparatus for the automated generation of single and multistage programmable interconnect matrices with automatic routing tools

• US 6,467,073 B1
• Filed: 11/30/1999
• Issued: 10/15/2002
• Est. Priority Date: 12/10/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Merchant, James D.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/451,959
• Time in Patent Office: 1,050 Days
• Field of Search: 716/2, 716/5, 716/16, 716/17, 738/635.3
• US Class Current: 716/103
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method to automatically generate a single and/or multistage PIM, comprising the steps of (A) generating a schematic that matches a layout of the PIM, (B) optionally generating a first stage and a second stage for the PIM, depending on one or more electronic and/or physical properties of the PIM and (C) automatically placing and connecting a non-regular structure at an input and/or output of a stage of the PIM.

Claims

1. A method to automatically generate a single and/or multistage Programmable Interconnect Matrix (PIM), comprising the steps of:

(A) generating a schematic that matches a layout of the PIM,

(B) optionally generating a first stage and a second stage for the PIM, depending on one or more electronic and/or physical properties of the PIM, and

(C) automatically placing and connecting a non-regular structure at an input and/or output of a stage of the PIM, wherein said PIM comprises a multiplexer coupled between the input and the output of each stage of the PIM.

2. The method according to claim 1, wherein at least one of the steps is performed with an automatic router.

3. The method according to claim 2, wherein said automatic router is configured to route signals and place contacts.

4. The method according to claim 2, wherein said automatic router is configured to hierarchically create a single stage and or multistage layout with or without additional buffers.

5. The method according to claim 1, wherein the number of possible inputs available to a PIM bit is variable.

6. The method according to claim 1, wherein at least one electronic and/or physical property of the PIM determines that the PIM will contain multiple stages and the method comprises generating the first and second stages of the PIM.

7. The method according to claim 1, wherein said PIM comprises one or more arrays of single-bit multiplexers, wherein each multiplexer is independently enabled by a control signal.

8. The method according to claim 1, wherein said method increases a maximum number of inputs available to the PIM.

9. The method according to claim 1, wherein one of said non-regular structures comprises one or more buffers configured to adjust drive strengths.

10. The method according to claim 1, further comprising the step of:

creating multiple PIM bit cells and/or additional feed through cells.

11. The method according to claim 1, wherein step (A) places arrays of PIM bits with named wire connections as defined by a PIM application.

12. The method according to claim 1, further comprising the step of:

defining routing channels and connection points for layout pinning.

13. The method according to claim 1, wherein said non-regular structure is selected from group consisting of buffers, drivers, logic gates and other cells.

14. A circuit comprising:

means for generating a schematic that matches a programmable interconnect matrix (PIM) layout;

means for generating a single and/or multistage PIM; and

means for automatically placing and connecting a non-regular structure at an input and/or output of a stage of the a PIM, wherein said PIM comprises a multiplexer coupled between the input and the output of each stage of the PIM.

15. The circuit according to claim 14, further comprising an automatic router configured to generate one or more of (i) said layout, (ii) said non-regular structure and (iii) said single and/or multistage PIM.

16. The circuit according to claim 14, wherein at least one electronic and/or physical property of the PIM determines that the PIM will contain multiple stages.

17. The circuit according to claim 14, wherein said circuit increases the maximum number of inputs available to the PIM.

18. The circuit according to claim 14, further comprising:

means for creating multiple PIM bit cells and additional feed through cells.

19. A computer readable medium for storing instructions to automatically generate a single and/or multistage Programmable Interconnect Matrix (PIM), comprising the steps of:

(A) generating a schematic that matches a layout of the PIM,

(B) optionally generating a first stage and a second stage for the PIM, depending on one or more properties of the PIM, and

(C) automatically placing and connecting a structure at an input and/or output of a stage of the PIM, wherein said PIM comprises a multiplexer coupled between the input and the output of each stage of the PIM.