Method of fabricating a high-voltage transistor

• US 6,468,847 B1
• Filed: 11/27/2000
• Issued: 10/22/2002
• Est. Priority Date: 11/27/2000
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/723,957
• Time in Patent Office: 694 Days
• Field of Search: 438/186, 438/188, 438/197, 438/199, 438/301, 438/305, 438/306, 438/526, 438/527, 438/529
• US Class Current: 438/197
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Claims

1. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

successively implanting a first dopant of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface of the first substrate source to form a first plurality of buried layers, each of the first plurality of buried layers being of the first conductivity type and disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type are formed within the first substrate;

bonding the first surface of the first substrate to a second substrate of the first of conductivity type;

thinning the first substrate from the second surface;

successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers, each of the second plurality of buried layers being of the first conductivity type and disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type are formed within the first substrate.

2. The method according to claim 1 wherein the first and second dopants are identical.

3. The method according to claim 1 wherein the first and second dopants comprise boron.

4. The method according to claim 1 wherein each of the first plurality of buried layers is spaced apart from the first surface.

5. The method according to claim 4 wherein each of the second plurality of buried layers is spaced apart from the second surface.

6. The method according to claim 1 wherein thinning is performed by etching back the second surface to an etch stop layer or cleave plane embedded within the first substrate.

7. The method according to claim 1 wherein the first and second JFET conduction channels are formed in a parallel configuration.

8. The method according to claim 1 wherein the first conductivity type is P-type and the second conductivity type is N-type.

9. The method according to claim 1 wherein the second plurality of buried layers are spaced vertically apart from the first plurality of buried layers.

10. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

forming a well region of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, the well region having a laterally extended portion with a lateral boundary;

successively implanting a first dopant of the second conductivity type in the well region, each implant being performed at a different energy through the first surface to form a first plurality of buried layers within the laterally extended portion of the well region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the first conductivity type is formed within the first substrate;

bonding the first surface of the first substrate to a second substrate of the second conductivity type;

thinning the first substrate from the second surface;

successively implanting a second dopant of the second conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended portion of the well region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed within the first substrate.

11. The method according to claim 10 wherein the first and second dopants are identical.

12. The method according to claim 10 wherein each of the first plurality of buried layers is spaced apart from the first surface.

13. The method according to claim 12 wherein each of the second plurality of buried layers is spaced apart from the second surface.

14. The method according to claim 10 wherein thinning is performed by etching back the second surface to an etch stop layer or cleave plane embedded within the first substrate.

15. The method according to claim 10 wherein the first conductivity type is N-type and the second conductivity type is P-type.

16. The method according to claim 10 wherein the first and second plurality of buried layers are spaced-apart from the lateral boundary.

17. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

successively implanting a first dopant of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface to form a first plurality of buried layers in a laterally extended region and a second plurality of buried layers in a source region of the first substrate, each of the first and second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region, a section of the source region being partially masked at the first surface such that the second plurality of buried layers in the source region is formed into a first continuous doped region;

bonding the first surface of the first substrate to a second substrate of the first conductivity type;

thinning the first substrate from the second surface;

successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a third plurality of buried layers within the laterally extended region and a fourth plurality of buried layers in the source region of the first substrate, each of the third and fourth plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region, the section of the source region being partially masked at the second surface such that the fourth plurality of buried layers in the source region is formed into a second continuous doped region, wherein the first and second continuous doped regions are connected to form a single continuous doped region that extends to the second substrate;

forming a gate insulated from the first substrate by a gate oxide layer, the gate extending over the second surface adjacent the laterally extended region of the first substrate;

forming a body region of the first conductivity type connected to the single continuous doped region in the first substrate, the body region adjoining the second surface and having a lateral boundary that extends beneath the gate;

forming a source diffusion region of the second conductivity type in the body region spaced-apart from the lateral boundary, a channel region being formed in the body region between the source diffusion region and the lateral boundary; and

forming a drain diffusion region of the second conductivity type in the first substrate at a side of the laterally extended region opposite the source diffusion region.

18. The method according to claim 17 further comprising the step of:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

19. The method according to claim 17 wherein each of the third plurality of buried layers is spaced apart from the second surface.

20. The method according to claim 17 wherein thinning is performed by etching back the second surface to an etch stop layer or cleave plane embedded within the first substrate.

21. The method according to claim 17 wherein the third plurality of buried layers is spaced-apart from the lateral boundary.

22. The method according to claim 17 wherein the first and third plurality of buried layers are spaced-apart from the single continuous doped region.

23. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

successively implanting a first dopant of the first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface to form a first plurality of buried layers in a laterally extended region of the first substrate, each of the first plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;

bonding the first surface of the first substrate to a second substrate of the first conductivity type;

thinning the first substrate from the second surface;

successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended region, each of second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;

forming a gate insulated from the first substrate by a gate oxide layer, the gate extending over the second surface adjacent the laterally extended region of the first substrate;

forming a body region of the first conductivity type in the first substrate, the body region adjoining the second surface and having a lateral boundary that extends beneath the gate;

forming a source diffusion region of the second conductivity type in the body region spaced-apart from the lateral boundary, a channel region being formed in the body region between the source diffusion region and the lateral boundary; and

forming a drain diffusion region of the first conductivity type in the first substrate on a side of the laterally extended region opposite the source diffusion region.

24. The method according to claim 23 further comprising the step of:

initially forming a deep diffusion region of the first conductivity type in the first substrate, each of the first and second plurality of buried layers being subsequently formed spaced apart from the deep diffusion region,

wherein the deep diffusion is connected to the second substrate following bonding and also to the body region following formation of the body region.

25. The method according to claim 23 further comprising:

forming a trench isolation region in the first substrate extending from the first surface to the second surface to electrically isolate the HVFET from other circuitry.

26. The method according to either claim 24 or 25, wherein thinning is performed by etching back the second surface to an etch stop layer or cleave plane embedded within the first substrate.

27. The method according to either claim 24 or 25, wherein the second plurality of buried layers is spaced-apart from the lateral boundary.

28. The method according to either claims 24 or 25, further comprising:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

29. The method according to claim 25 wherein the trench isolation region is formed after thinning of the first substrate.

30. The method according to either claims 23, 24 or 25, wherein the drain diffusion region is formed by:

etching a trench into the first substrate on the side of the laterally extended region;

forming a drain diffusion region that extends laterally from the trench so as to provide uniform current flow through the first and second JFET conduction channels.

31. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

successively implanting a first dopant of the first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface to form a first plurality of buried layers in a laterally extended region of the first substrate, each of the first plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;

bonding the first surface of the first substrate to a second substrate of the first conductivity type;

thinning the first substrate from the second surface;

successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended region, each of second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;

forming a trench gate insulated from the first substrate by a gate oxide layer that extends vertically from the second surface of the first substrate adjacent one side of the laterally extended region;

forming a body region of the first conductivity type in the first substrate, the body region adjoining the second surface and the gate oxide;

forming a source diffusion region of the second conductivity type in the body region adjacent the gate oxide, a vertical channel region being formed in the body region between the source diffusion region and the first substrate near the gate oxide; and

forming a drain diffusion region of the first conductivity type in the first substrate on a side of the laterally extended region opposite the source diffusion region.

32. The method according to claim 31, wherein thinning is performed by etching back the second surface to an etch stop layer or cleave plane embedded within the first substrate.

33. The method according to claim 31, further comprising:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

34. The method according to claim 31, wherein the drain diffusion region is formed by:

etching a trench into the first substrate on the side of the laterally extended region opposite the source diffusion region;

forming a drain diffusion region that extends laterally from the trench so as to provide uniform current flow through the first and second JFET conduction channels.

35. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

forming a well region of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, the well region having a laterally extended portion with a lateral boundary;

successively implanting a first dopant of the second conductivity type in the well region, each implant being performed at a different energy through the first surface to form a first plurality of buried layers within the laterally extended portion of the well region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the first conductivity type is formed within the first substrate;

bonding the first surface of the first substrate to a second substrate of the second conductivity type;

thinning the first substrate from the second surface;

successively implanting a second dopant of the second conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended portion of the well region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed within the first substrate;

forming a gate insulated from the substrate by a gate oxide layer, the gate extending over the second surface of the first substrate adjacent the laterally extended portion of the well region;

forming a body region of the second conductivity type in the first substrate, the body region adjoining the second surface and extending across the lateral boundary into the well region beneath the gate;

implanting a dopant of the first conductivity type in the body region to form a source diffusion region spaced-apart from the well region, and also into the well region to form a drain diffusion region, a channel region being formed in the body region between the source diffusion region and the well region under the gate; and

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

36. The method according to claim 35 wherein the first and second dopants are identical.

37. The method according to claim 35 wherein each of the first plurality of buried layers is spaced apart from the first surface.

38. The method according to claim 37 wherein each of the second plurality of buried layers is spaced apart from the second surface.

39. The method according to claim 35 wherein thinning is performed by etching back the second surface to an etch stop layer or cleave plane embedded within the first substrate.

40. The method according to claim 35 wherein the first conductivity type is N-type and the second conductivity type is P-type.

41. The method according to claim 35 wherein the first and second plurality of buried layers are spaced-apart from the lateral boundary.