Method of forming a metal insulator metal capacitor structure
First Claim
1. A method of fabricating a metal—
- insulator—
metal (MIM), capacitor structure on a semiconductor substrate, comprising the steps of;
providing a conductive plug structure, located in an opening in a first interlevel dielectric (ILD), layer, overlying and contacting a source/drain region of a transfer gate transistor;
forming a composite landing pad structure on said first ILD layer, and on the top surface of said conductive plug structure, with said composite landing pad structure comprised with an overlying ruthenium layer;
depositing a second ILD layer, and an overlying silicon nitride layer;
forming a storage node contact hole in said silicon nitride layer, and in said second ILD layer, exposing a portion of the top surface of said ruthenium layer;
forming a platinum plug structure in said storage node contact hole;
forming a capacitor opening in a third ILD layer, exposing the top surface of said platinum plug structure, located at the bottom of said capacitor opening;
forming silicon nitride spacers on the sides of said capacitor opening;
forming a metal storage node structure on exposed surfaces of said capacitor opening, overlying and contacting the top surface of said platinum plug structure;
forming a high dielectric constant (high k), layer on said metal storage structure; and
forming a metal top plate structure on said high k layer, resulting in said MIM capacitor structure comprised of said metal top plate structure, said high k layer, and said metal storage node structure.
1 Assignment
0 Petitions
Accused Products
Abstract
A process for forming a metal—insulator—metal (MIM), capacitor structure, in which platinum is employed for both the capacitor top plate and storage node structures, while a high dielectric constant layer, such as BaTiO3 is used for the capacitor dielectric layer, has been developed. Prior to formation of the MIM capacitor structure, an underlying, platinum storage node plug structure is formed in a narrow diameter opening, allowing communication between the MIM capacitor structure, and regions of an underlying transfer gate transistor, to be realized. A thin ruthenium shape is used as a seed layer to allow an electroless plating procedure to be employed for attainment of the platinum storage node plug structure.
56 Citations
24 Claims
-
1. A method of fabricating a metal—
- insulator—
metal (MIM), capacitor structure on a semiconductor substrate, comprising the steps of;providing a conductive plug structure, located in an opening in a first interlevel dielectric (ILD), layer, overlying and contacting a source/drain region of a transfer gate transistor;
forming a composite landing pad structure on said first ILD layer, and on the top surface of said conductive plug structure, with said composite landing pad structure comprised with an overlying ruthenium layer;
depositing a second ILD layer, and an overlying silicon nitride layer;
forming a storage node contact hole in said silicon nitride layer, and in said second ILD layer, exposing a portion of the top surface of said ruthenium layer;
forming a platinum plug structure in said storage node contact hole;
forming a capacitor opening in a third ILD layer, exposing the top surface of said platinum plug structure, located at the bottom of said capacitor opening;
forming silicon nitride spacers on the sides of said capacitor opening;
forming a metal storage node structure on exposed surfaces of said capacitor opening, overlying and contacting the top surface of said platinum plug structure;
forming a high dielectric constant (high k), layer on said metal storage structure; and
forming a metal top plate structure on said high k layer, resulting in said MIM capacitor structure comprised of said metal top plate structure, said high k layer, and said metal storage node structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 20)
- insulator—
-
10. A method of fabricating a metal—
- insulator—
metal (MIM), capacitor structure on an underlying electroless plated, platinum storage node plug structure, comprising the steps of;providing a transfer gate transistor comprised of a gate structure on an underlying gate insulator layer, with a source/drain region located in an area of a semiconductor substrate not covered by the gate structure;
depositing a first interlevel dielectric (ILD), layer;
forming a contact hole opening in said first ILD layer exposing a portion of the top surface of said source/drain region;
forming a doped polysilicon plug structure in said contact hole opening;
depositing a tungsten layer;
depositing a thin ruthenium layer;
patterning said thin ruthenium layer, and said tungsten layer, to define a landing pad structure located on said first ILD layer, and on the top surface of said doped polysilicon plug structure, with said landing pad structure comprised of a ruthenium seed shape on an underlying tungsten shape;
depositing a second ILD layer;
planarizing said second ILD layer;
depositing a silicon nitride layer;
forming a storage node contact hole in said silicon nitride layer and in said second ILD layer, exposing a portion of the top surface of said ruthenium seed shape;
performing an electroless plating procedure to form said platinum storage node plug structure in said storage node contact hole;
depositing a third ILD layer;
forming a capacitor opening in said third ILD layer, exposing the top surface of said platinum storage node plug structure;
forming silicon nitride spacers on the sides of said capacitor structure;
depositing a first platinum layer;
performing a chemical mechanical polishing procedure to remove portions of said first platinum layer from the top surface of said third ILD layer resulting in formation of a platinum storage node structure in said capacitor opening, overlying and contacting the top surface of said platinum storage node plug structure;
depositing a BaTiO3 layer;
depositing a second platinum layer; and
patterning of said second platinum layer, and of said BaTiO3 layer, to form said MIM capacitor structure, comprised of a top plate defined from said second platinum layer, comprised of a capacitor dielectric featuring BaTiO3, and comprised of said platinum storage node structure. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24)
- insulator—
Specification