Method and device for producing undercut gate for flash memory

• US 6,469,341 B1
• Filed: 07/25/2000
• Issued: 10/22/2002
• Est. Priority Date: 05/11/1998
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Sung, Kuo-Tung, Lee, Ray C.
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/625,143
• Time in Patent Office: 819 Days
• Field of Search: 257/315, 257/316, 257/321
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a “tunnel oxide” layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.

Claims

1. A semiconductor device, said device comprising:

a substrate, said substrate including a layer of dielectric material overlying an active region; and

a floating gate overlying said layer of dielectric material, said floating gate including a side wall having a slant edge, said slant edge defining a generally concave-shaped undercut edge, and wherein said side wall comprises substantially vertical edges above said slant edge.

2. The device of claim 1 wherein said floating gate layer comprises polysilicon.

3. The device of claim 1 further comprising a dielectric layer overlying said floating gate layer.

4. The device of claim 3 wherein said dielectric layer comprises a nitride layer, said nitride layer being sandwiched between oxide layers.

5. The device of claim 3 further comprising a control gate overlying said floating gate, said control gate being capacitively coupled to said floating gate through said dielectric layer.

6. The device of claim 1 wherein said floating gate layer comprises a first surface overlying said dielectric material and a second surface facing said dielectric layer.

7. The device of claim 1 wherein said second surface has a greater surface area than said first surface.

8. The device of claim 1 wherein said second surface has a greater surface area than said first surface by at least 30 percent.

9. The device of claim 1 wherein said slant edges are provided by an etching process, said etching process being selected from isotropic etching and plasma scattering etching.

11. The device of claim 3 further comprising a control gate at least partially overlying said floating gate, said control gate being capacitively coupled to said floating gate through said dielectric layer.

12. The device of claim 3 further comprising a control gate at least partially overlying said floating gate and partially overlying said substrate.

13. The device of claim 1 wherein said floating gate comprises a split floating gate.

14. The device of claim 13 further comprising a select gate overlying said substrate, said split floating gate partially overlying said substrate and partially overlying said select gate.

16. The device as in claim 1 wherein said undercut edge is visible in a cross-sectional depiction through a bit line of said device.

10. In a semiconductor memory device, wherein the device includes a substrate, and said substrate includes a layer of dielectric material overlying an active region, a floating gate overlying said layer of dielectric material, said floating gate comprising:

a first surface overlying said layer of dielectric material and a second surface spaced apart from the first surface defining a sidewall therebetween;

said side wall having a substantially linear portion extending from the second surface and a slant edge extending from the substantially linear portion to the first surface, said slant edge defining a rounded, generally concave-shaped undercut edge.

18. The device as in claim 10 wherein the substantially linear portion comprises a substantially vertical linear portion.

15. A semiconductor device, said device comprising:

a substrate having an active region;

a layer of dielectric material overlying said active region; and

a floating gate layer overlying said layer of dielectric material, said floating gate layer comprising,

a first surface overlying said dielectric material and adjacent a channel region of said substrate, said first surface having a first surface area;

a second surface facing said layer of dielectric material, said second surface having a second surface area, said first surface and said second surface being spaced apart to form at least one floating gate layer side wall, said side wall having at least a portion comprising a slant edge;

wherein said side wall slant edge comprises a generally concave-shaped undercut edge;

wherein said side wall comprises a generally vertical portion from said second surface to a position intermediate said first and second surfaces, said slant edge extending from said position intermediate to said first surface; and

wherein said side wall slant edge reduces said first surface area to an amount that is less than said second surface area to increase a gate coupling ratio towards 1 (one).

17. The device as in claim 15 wherein said slant edge extends from about said second surface to said first surface.