Unmolded package for a semiconductor device

• US 6,469,384 B2
• Filed: 02/01/2001
• Issued: 10/22/2002
• Est. Priority Date: 02/01/2001
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US09/776,341
• Publication Number:
  US 20020100962A1
• Time in Patent Office: 628 Days
• Field of Search: 257/723, 257/737, 257/738, 257/758
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Claims

1. A semiconductor device comprising:

a substrate;

a die coupled to the substrate, the die comprising drain, source and gate regions; and

multiple solder balls coupled to the substrate adjacent the die, the solderballs being substantially coplanar with a surface of the die upon coupling the semiconductor device to a printed circuit board and providing communication between the source region and the printed circuit board;

wherein the die is substantially free of underfilling material around its periphery.

2. A semiconductor device in accordance with claim 1 wherein the substrate comprises a base layer, a metal layer and an insulating layer between the base layer and the metal layer.

3. A semiconductor device in accordance with claim 2 wherein the base layer comprises a metallized pattern and the metal layer comprises a second metallized pattern.

4. A semiconductor device in accordance with claim 1 wherein the base layer comprises a metallized ceramic.

5. A semiconductor device in accordance with claim 4 wherein the metallized ceramic comprises at least one layer of metallization.

6. A semiconductor device in accordance with claim 1 further comprising a second die coupled to the substrate on a surface opposite a surface to which the first die is coupled.