Reconfigurable device having programmable interconnect network suitable for implementing data paths

• US 6,469,540 B2
• Filed: 06/14/2001
• Issued: 10/22/2002
• Est. Priority Date: 06/15/2000
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakaya, Shogo
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/880,018
• Publication Number:
  US 20010052793A1
• Time in Patent Office: 495 Days
• Field of Search: 326/38-41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A reconfigurable device includes a plurality of function cells and a programmable interconnect network which programmably connects the function cells. The programmable interconnect network includes horizontal programmable interconnect ways and vertical programmable interconnect ways. Each horizontal programmable interconnect way includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and each vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel. In the horizontal programmable interconnect way, both the short horizontal programmable interconnect channel and the long horizontal programmable interconnect channel are constructed to have “shift structure”, thereby “sector segmentation” and problems related to the sector segmentation are avoided. The function cells are directly connected to the short horizontal programmable interconnect channel, but are not directly connected to the long horizontal programmable interconnect channel, therefore, signal transfer of input/output signals between the function cell and the long horizontal programmable interconnect channel is conducted necessarily through the short horizontal programmable interconnect channel and a programmable switch, thereby load capacitance on the long horizontal programmable interconnect channel is reduced and thereby high-speed signal transfer is realized.

Claims

1. A reconfigurable integrated circuit device comprising a plurality of function cells and a programmable interconnect network which programmably connects said plurality of function cells, wherein:

a plurality of tiles are disposed in a two-dimensional array which extends in a horizontal direction and a vertical direction, and

each of said plurality of tiles includes one of said plurality of function cells and part of said programmable interconnect network in the vicinity of the function cell, and

each said plurality of function cells includes;

a function block having first input terminals, one or more first output terminals, and functions from which a function is programmably selected and set thereto, for generating an output signal from signals supplied to the first input terminals according to the function which has been set thereto and outputting the generated output signal from the one or more first output terminals;

input selection each of which has second input terminals and a second output terminal, for programmably setting one of the second input terminals to be connected to the second output terminal;

an output selection switch having a third input terminal and third output terminals, for programmably setting each of the third output terminals to be connected to the third input terminal or to be in high impedance status; and

input/output lines which are connected to the second input terminals of the input selection switches and the third output terminals of the output selection switch, and

said second output terminal is connected to said first input terminal, and said third input terminal is connected to said first output terminal, and

the programmable interconnect network includes horizontal programmable interconnect ways each of which runs in the horizontal direction in each row of the two-dimensional array respectively, and

the horizontal programmable interconnect way includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and

the short horizontal programmable interconnect channel includes M short horizontal lanes (M;

natural number) each of which includes short horizontal programmable switches which are provided to every M tiles aligned in the horizontal direction and short horizontal interconnect line segments as seamless lines connecting adjacent short horizontal programmable switches, and

the horizontal positions of tiles containing the short horizontal programmable switches of each short horizontal lane of the short horizontal programmable interconnect channel are successively shifted between adjacent short horizontal lanes by 1 tile width, and

the long horizontal programmable interconnect channel includes M long horizontal lanes each of which includes long horizontal programmable switches which are provided to every N tiles (N;

natural number) aligned in the horizontal direction and long horizontal interconnect line segments as seamless lines connecting adjacent long horizontal programmable switches, and

the horizontal positions of tiles containing the long horizontal programmable switches of each long horizontal lane of the long horizontal programmable interconnect channel are successively shifted between adjacent long horizontal lanes by P tile widths (P;

natural number≧

4, P=N/M), and

each short horizontal interconnect line segment is connected to one of the long horizontal interconnect line segments through an inter-horizontal-channel programmable switch which is provided to each tile, and

long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary M contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes, and

each input/output line of the function cell is directly connected to corresponding one of the short horizontal interconnect line segments running in the tile containing the function cell, and

each of the programmable switches programmably connects/disconnects the connection between the line segments that are connected thereto.

2. The reconfigurable device as claimed in claim 1, wherein:

each column of the two-dimensional array is divided into ALUs (Arithmetic and Logic Units) each of which is composed of U contiguous tiles (U;

natural number) of the column, and

the function cells contained in the ALU share at least one of input signals on said first input terminals, signals on said second input terminals and configuration data determining the functions of said function blocks and said input selection switches, and

the programmable interconnect network further includes vertical programmable interconnect ways each of which runs in the vertical direction in each column of the two-dimensional array respectively, and

the vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel, and

the short vertical programmable interconnect channel includes W short vertical lanes (W;

natural number<

M) each of which includes short vertical programmable switches which are provided to every V tiles (V;

integral multiple of U) aligned in the vertical direction and short vertical interconnect line segments as seamless lines connecting adjacent short vertical programmable switches, and

at least one of the W short horizontal lanes of the short vertical programmable interconnect channel is composed of short vertical interconnect line segments each of which seamlessly stretches from the uppermost tile to the lowermost tile of an ALU, and

the long vertical programmable interconnect channel includes L long vertical lanes (L;

natural number≦

W) each of which is composed of long vertical interconnect line segments whose lengths are at least 4 times as long as the short vertical interconnect line segment, and

each short vertical interconnect line segment is connected to one of the long vertical interconnect line segment through an inter-vertical-channel programmable switch, and

each short vertical interconnect line segment is connected to one of the short horizontal interconnect line segments intersecting the short vertical interconnect line segment in each row of the two-dimensional array through an intersection programmable switch.

3. The reconfigurable device as claimed in claim 1, wherein the natural numbers M and P are relatively prime.

4. The reconfigurable device as claimed in claim 2, wherein the natural numbers M and P are relatively prime.

5. A reconfigurable integrated circuit device comprising a plurality of function cells and a programmable interconnect network which programmably connects said plurality of function cells, wherein:

a plurality of tiles are disposed in a two-dimensional array which extends in a horizontal direction and a vertical direction, and

each of said plurality of tiles includes one of said plurality of function cells and part of said programmable interconnect network in the vicinity of the function cell, and

each said plurality of function cells includes;

a function block having first input terminals, one or more first output terminals, and functions from which a function is programmably selected and set thereto, for generating an output signal from signals supplied to the first input terminals according to the function which has been set thereto and outputting the generated output signal from the one or more first output terminals;

input selection switches each of which has second input terminals and a second output terminal, for programmably setting one of the second input terminals to be connected to the second output terminal;

an output selection switch having a third input terminal and third output terminals, for programmably setting each of the third output terminals to be connected to the third input terminal or to be in high impedance status; and

input/output lines which are connected to the second input terminals of the input selection switches and the third output terminals of the output selection switch, and

said second output terminal is connected to said first input terminal, and said third input terminal is connected to said first output terminal, and

the programmable interconnect network has two or more parallelly running horizontal programmable interconnect ways in each row of the two-dimensional array, and

each of the horizontal programmable interconnect ways includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and

the short horizontal programmable interconnect channel includes M short horizontal lanes (M;

natural number) each of which includes short horizontal programmable switches which are provided to every M tiles aligned in the horizontal direction and short horizontal interconnect line segments as seamless lines connecting adjacent short horizontal programmable switches, and

the horizontal positions of tiles containing the short horizontal programmable switches of each short horizontal lane of the short horizontal programmable interconnect channel are successively shifted between adjacent short horizontal lanes by 1 tile width, and

the long horizontal programmable interconnect channel includes M long horizontal lanes each of which includes long horizontal programmable switches which are provided to every N tiles (N;

natural number) aligned in the horizontal direction and long horizontal interconnect line segments as seamless lines connecting adjacent long horizontal programmable switches, and

the horizontal positions of tiles containing the long horizontal programmable switches of each long horizontal lane of the long horizontal programmable interconnect channel are successively shifted between adjacent long horizontal lanes by P tile widths (P;

natural number≧

4, P=N/M), and

in each horizontal programmable interconnect way, each short horizontal interconnect line segment is connected to one of the long horizontal interconnect line segments of the horizontal programmable interconnect way through an inter-horizontal-channel programmable switch which is provided to each tile, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary M contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes, and

each input/output line of the function cell is directly connected to corresponding one of the short horizontal interconnect line segments running in the tile containing the function cell, and

each of the programmable switches programmably connects/disconnects the connection between the line segments that are connected thereto.

6. The reconfigurable device as claimed in claim 5, wherein:

each column of the two-dimensional array is divided into ALUs (Arithmetic and Logic Units) each of which is composed of U contiguous tiles (U;

natural number) of the column, and

the function cells contained in the ALU share at least one of input signals on said first input terminals, signals on said second input terminals and configuration data determining the functions of said function blocks and said input selection switches, and

the programmable interconnect network further includes vertical programmable interconnect ways each of which runs in the vertical direction in each column of the two-dimensional array respectively, and

the vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel, and

the short vertical programmable interconnect channel includes W short vertical lanes (W;

natural number<

M) each of which includes short vertical programmable switches which are provided to every V tiles (V;

integral multiple of U) aligned in the vertical direction and short vertical interconnect line segments as seamless lines connecting adjacent short vertical programmable switches, and

at least one of the W short horizontal lanes of the short vertical programmable interconnect channel is composed of short vertical interconnect line segments each of which seamlessly stretches from the uppermost tile to the lowermost tile of an ALU, and

the long vertical programmable interconnect channel includes L long vertical lanes (L;

natural number≦

W) each of which is composed of long vertical interconnect line segments whose lengths are at least 4 times as long as the short vertical interconnect line segment, and

each short vertical interconnect line segment is connected to one of the long vertical interconnect line segment through an inter-vertical-channel programmable switch, and

each short vertical interconnect line segment is connected to one of the short horizontal interconnect line segments intersecting the short vertical interconnect line segment in each row of the two-dimensional array through an intersection programmable switch, and

intersection programmable switches that are contained in the same tile is connected to different short horizontal interconnect line segments.

7. The reconfigurable device as claimed in claim 5, wherein the natural numbers M and P are relatively prime.

8. The reconfigurable device as claimed in claim 6, wherein the natural numbers M and P are relatively prime.

9. The reconfigurable device as claimed in claim 5, wherein the horizontal positions of the long horizontal programmable switches in each horizontal programmable interconnect way are shifted between at least two of the two or more horizontal programmable interconnect ways parallelly running in each row of the two-dimensional array by a tile width or more.

10. The reconfigurable device as claimed in claim 6, wherein the horizontal positions of the long horizontal programmable switches in each horizontal programmable interconnect way are shifted between at least two of the two or more horizontal programmable interconnect ways parallelly running in each row of the two-dimensional array by a tile width or more.

11. The reconfigurable device as claimed in claim 9, wherein the natural numbers M and P are relatively prime.

12. The reconfigurable device as claimed in claim 10, wherein the natural numbers M and P are relatively prime.

13. The reconfigurable device as claimed in claim 5, wherein the horizontal positions of the long horizontal programmable switches in each horizontal programmable interconnect way are successively shifted between adjacent ones of the two or more horizontal programmable interconnect ways parallelly running in each row of the two-dimensional array by a tile width or more.

14. The reconfigurable device as claimed in claim 6, wherein the horizontal positions of the long horizontal programmable switches in each horizontal programmable interconnect way are successively shifted between adjacent ones of the two or more horizontal programmable interconnect ways parallelly running in each row of the two-dimensional array by a tile width or more.

15. The reconfigurable device as claimed in claim 13, wherein the natural numbers M and P are relatively prime.

16. The reconfigurable device as claimed in claim 14, wherein the natural numbers M and P are relatively prime.

17. A reconfigurable integrated circuit device comprising a plurality of function cells and a programmable interconnect network which programmably connects said plurality of function cells, wherein:

a plurality of tiles are disposed in a two-dimensional array which extends in a horizontal direction and a vertical direction, and

each of said plurality of tiles includes one of said plurality of function cells and part of said programmable interconnect network in the vicinity of the function cell, and

each said plurality of function cells includes;

a function block having first input terminals, one or more first output terminals, and functions from which a function is programmably selected and set thereto, for generating an output signal from signals supplied to the first input terminals according to the function which has been set thereto and outputting the generated output signal from the one or more first output terminals;

input selection switches each of which has second input terminals and a second output terminal, for programmably setting one of the second input terminals to be connected to the second output terminal;

an output selection switch having a third input terminal and third output terminals, for programmably setting each of the third output terminals to be connected to the third input terminal or to be in high impedance status; and

input/output lines which are connected to the second input terminals of the input selection switches and the third output terminals of the output selection switch, and

said second output terminal is connected to said first input terminal, and said third input terminal is connected to said first output terminal, and

the programmable interconnect network has two or more parallelly running horizontal programmable interconnect ways in each row of the two-dimensional array, and

each of the horizontal programmable interconnect ways includes a short horizontal programmable interconnect channel, and

each of part of the horizontal programmable interconnect ways further includes a long horizontal programmable interconnect channel, and

the short horizontal programmable interconnect channel includes M short horizontal lanes (M;

natural number) each of which includes short horizontal programmable switches which are provided to every M tiles aligned in the horizontal direction and short horizontal interconnect line segments as seamless lines connecting adjacent short horizontal programmable switches, and

the horizontal positions of tiles containing the short horizontal programmable switches of each short horizontal lane of the short horizontal programmable interconnect channel are successively shifted between adjacent short horizontal lanes by 1 tile width, and

the long horizontal programmable interconnect channel includes M long horizontal lanes each of which includes long horizontal programmable switches which are provided to every N tiles (N;

natural number) aligned in the horizontal direction and long horizontal interconnect line segments as seamless lines connecting adjacent long horizontal programmable switches, and

the horizontal positions of tiles containing the long horizontal programmable switches of each long horizontal lane of the long horizontal programmable interconnect channel are successively shifted between adjacent long horizontal lanes by P tile widths (P;

natural number≧

4, P=N/M), and

in each horizontal programmable interconnect way that includes a long horizontal programmable interconnect channel, each short horizontal interconnect line segment is connected to one of the long horizontal interconnect line segments of the horizontal programmable interconnect way through an inter-horizontal-channel programmable switch which is provided to each tile, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary M contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes, and

each input/output line of the function cell is directly connected to corresponding one of the short horizontal interconnect line segments running in the tile containing the function cell, and

each of the programmable switches programmably connects/disconnects the connection between the line segments that are connected thereto.

18. The reconfigurable device as claimed in claim 17, wherein:

each column of the two-dimensional array is divided into ALUs (Arithmetic and Logic Units) each of which is composed of U contiguous tiles (U;

natural number) of the column, and

the function cells contained in the ALU share at least one of input signals on said first input terminals, signals on said second input terminals and configuration data determining the functions of said function blocks and said input selection switches, and

the programmable interconnect network further includes vertical programmable interconnect ways each of which runs in the vertical direction in each column of the two-dimensional array respectively, and

the vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel, and

the short vertical programmable interconnect channel includes W short vertical lanes (W;

natural number<

M) each of which includes short vertical programmable switches which are provided to every V tiles (V;

integral multiple of U) aligned in the vertical direction and short vertical interconnect line segments as seamless lines connecting adjacent short vertical programmable switches, and

at least one of the W short horizontal lanes of the short vertical programmable interconnect channel is composed of short vertical interconnect line segments each of which seamlessly stretches from the uppermost tile to the lowermost tile of an ALU, and

the long vertical programmable interconnect channel includes L long vertical lanes (L;

natural number≦

W) each of which is composed of long vertical interconnect line segments whose lengths are at least 4 times as long as the short vertical interconnect line segment, and

each short vertical interconnect line segment is connected to one of the long vertical interconnect line segment through an inter-vertical-channel programmable switch, and

each short vertical interconnect line segment is connected to one of the short horizontal interconnect line segments intersecting the short vertical interconnect line segment in each row of the two-dimensional array through an intersection programmable switch, and

intersection programmable switches that are contained in the same tile is connected to different short horizontal interconnect line segments.

19. The reconfigurable device as claimed in claim 17, wherein the natural numbers M and P are relatively prime.

20. The reconfigurable device as claimed in claim 18, wherein the natural numbers M and P are relatively prime.

21. The reconfigurable device as claimed in claim 17, wherein in at least one horizontal programmable interconnect way that includes no long horizontal programmable interconnect channel, each short horizontal interconnect line segment is connected to a long horizontal interconnect line segment of a horizontal programmable interconnect way that includes a long horizontal programmable interconnect channel through an inter-horizontal-channel programmable switch which is provided to each tile, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary M contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes.

22. The reconfigurable device as claimed in claim 18, wherein in at least one horizontal programmable interconnect way that includes no long horizontal programmable interconnect channel, each short horizontal interconnect line segment is connected to a long horizontal interconnect line segment of a horizontal programmable interconnect way that includes a long horizontal programmable interconnect channel through an inter-horizontal-channel programmable switch which is provided to each tile, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary M contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes.

23. The reconfigurable device as claimed in claim 21, wherein the natural numbers M and P are relatively prime.

24. The reconfigurable device as claimed in claim 22, wherein the natural numbers M and P are relatively prime.

25. A reconfigurable integrated circuit device comprising a plurality of function cells and a programmable interconnect network which programmably connects said plurality of function cells, wherein:

a plurality of tiles are disposed in a two-dimensional array which extends in a horizontal direction and a vertical direction, and

each of said plurality of tiles includes one of said plurality of function cells and part of said programmable interconnect network in the vicinity of the function cell, and

each said plurality of function cells includes;

a function block having first input terminals, one or more first output terminals, and functions from which a function is programmably selected and set thereto, for generating an output signal from signals supplied to the first input terminals according to the function which has been set thereto and outputting the generated output signal from the one or more first output terminals;

input selection switches each of which has second input terminals and a second output terminal, for programmably setting one of the second input terminals to be connected to the second output terminal;

an output selection switch having a third input terminal and third output terminals, for programmably setting each of the third output terminals to be connected to the third input terminal or to be in high impedance status; and

input/output lines which are connected to the second input terminals of the input selection switches and the third output terminals of the output selection switch, and

said second output terminal is connected to said first input terminal, and said third input terminal is connected to said first output terminal, and

the programmable interconnect network has J parallelly running horizontal programmable interconnect ways (J;

natural number) in each row of the two-dimensional array, and

each of the J horizontal programmable interconnect ways includes a short horizontal programmable interconnect channel, and

each of K horizontal programmable interconnect ways (K;

natural number≦

J) selected out of the J horizontal programmable interconnect ways further includes a long horizontal programmable interconnect channel, and

in each j-th horizontal programmable interconnect way (j;

natural number≦

J) included in the J horizontal programmable interconnect ways, the short horizontal programmable interconnect channel includes Mj short horizontal lanes (Mj;

natural number) each of which includes short horizontal programmable switches which are provided to every Mj tiles aligned in the horizontal direction and short horizontal interconnect line segments as seamless lines connecting adjacent short horizontal programmable switches, and the horizontal positions of tiles containing the short horizontal programmable switches of each short horizontal lane are successively shifted between adjacent short horizontal lanes by 1 tile width, and

in each k-th horizontal programmable interconnect way (k;

natural number≦

K) included in the K horizontal programmable interconnect ways, the long horizontal programmable interconnect channel includes Mk long horizontal lanes (Mk;

natural number) each of which includes long horizontal programmable switches which are provided to every Nk tiles (Nk;

natural number) aligned in the horizontal direction and long horizontal interconnect line segments as seamless lines connecting adjacent long horizontal programmable switches, and the horizontal positions of tiles containing the long horizontal programmable switches of each long horizontal lane of the long horizontal programmable interconnect channel are successively shifted between adjacent long horizontal lanes by Pk tile widths (Pk;

natural number≧

4, Pk=Nk/Mk), and

at least two selected from the natural numbers Pk (k≦

K) are set to be different from each other, or at least two selected from the natural numbers Mk (k≦

K) are set to be different from each other, and

in each k-th horizontal programmable interconnect way (k≦

K) included in the K horizontal programmable interconnect ways, each short horizontal interconnect line segment is connected to one of the long horizontal interconnect line segments of the k-th horizontal programmable interconnect way through an inter-horizontal-channel programmable switch which is provided to each tile, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary Mk contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes, and

each input/output line of the function cell is directly connected to corresponding one of the short horizontal interconnect line segments running in the tile containing the function cell, and

each of the programmable switches programmably connects/disconnects the connection between the line segments that are connected thereto.

26. The reconfigurable device as claimed in claim 25, wherein:

each column of the two-dimensional array is divided into ALUs (Arithmetic and Logic Units) each of which is composed of U contiguous tiles (U;

natural number) of the column, and

the function cells contained in the ALU share at least one of input signals on said first input terminals, signals on said second input terminals and configuration data determining the functions of said function blocks and said input selection switches, and

the programmable interconnect network further includes vertical programmable interconnect ways each of which runs in the vertical direction in each column of the two-dimensional array respectively, and

the vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel, and

the short vertical programmable interconnect channel includes W short vertical lanes (W;

natural number<

Min (Mk)) each of which includes short vertical programmable switches which are provided to every V tiles (V;

integral multiple of U) aligned in the vertical direction and short vertical interconnect line segments as seamless lines connecting adjacent short vertical programmable switches, and

at least one of the W short horizontal lanes of the short vertical programmable interconnect channel is composed of short vertical interconnect line segments each of which seamlessly stretches from the uppermost tile to the lowermost tile of an ALU, and

the long vertical programmable interconnect channel includes L long vertical lanes (L;

natural number≦

W) each of which is composed of long vertical interconnect line segments whose lengths are at least 4 times as long as the short vertical interconnect line segment, and

each short vertical interconnect line segment is connected to one of the long vertical interconnect line segments through an inter-vertical-channel programmable switch, and

each short vertical interconnect line segment is connected to one of the short horizontal interconnect line segments intersecting the short vertical interconnect line segment in each row of the two-dimensional array through an intersection programmable switch, and

intersection programmable switches that are contained in the same tile is connected to different short horizontal interconnect line segments.

27. The reconfigurable device as claimed in claim 25, wherein the natural numbers Mk and Pk are relatively prime in at least one horizontal programmable interconnect way included in the K horizontal programmable interconnect ways.

28. The reconfigurable device as claimed in claim 26, wherein the natural numbers Mk and Pk are relatively prime in at least one horizontal programmable interconnect way included in the K horizontal programmable interconnect ways.

29. The reconfigurable device as claimed in claim 25, wherein in at least one horizontal programmable interconnect way that is not included in the K horizontal programmable interconnect ways, each short horizontal interconnect line segment is connected to a long horizontal interconnect line segment of a k-th horizontal programmable interconnect way that is included in the K horizontal programmable interconnect ways through an inter-horizontal-channel programmable switch, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary Mk contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes.

30. The reconfigurable device as claimed in claim 26, wherein in at least one horizontal programmable interconnect way that is not included in the K horizontal programmable interconnect ways, each short horizontal interconnect line segment is connected to a long horizontal interconnect line segment of a k-th horizontal programmable interconnect way that is included in the K horizontal programmable interconnect ways through an inter-horizontal-channel programmable switch, and long horizontal interconnect line segments to which the inter-horizontal-channel programmable switches of arbitrary Mk contiguous tiles aligned in the horizontal direction are connected belong to different long horizontal lanes.

31. The reconfigurable device as claimed in claim 29, wherein the natural numbers Mk and Pk are relatively prime in at least one horizontal programmable interconnect way included in the K horizontal programmable interconnect ways.

32. The reconfigurable device as claimed in claim 30, wherein the natural numbers Mk and Pk are relatively prime in at least one horizontal programmable interconnect way included in the K horizontal programmable interconnect ways.