Device and method for reducing idle cycles in a semiconductor memory device

• US 6,469,954 B1
• Filed: 08/21/2000
• Issued: 10/22/2002
• Est. Priority Date: 08/21/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, Joseph T., Wilford, John R.
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/642,355
• Time in Patent Office: 792 Days
• Field of Search: 365/233, 365/230.03, 365/230.02, 365/230.08, 365/189.04, 365/189.02, 365/189.05
• US Class Current: 365/233.16
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM'"'"'s array reads out the full N bits simultaneously, the array'"'"'s address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array'"'"'s address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

Claims

1. A method for performing memory operations in a semiconductor memory, the method comprising:

selecting an N-bit wide row of the semiconductor memory;

providing N-bit wide temporary storage in communication with the selected row; and

simultaneously transferring X, N/X-bit data portions between the selected row and the temporary storage, where X comprises a nonzero positive integer.

2. The method of claim 1, wherein selecting the N-bit wide row includes registering an externally generated address into the semiconductor memory.

3. The method of claim 1, wherein providing the N-bit wide temporary storage comprises at least one of providing N latched sense amplifiers in communication with the selected row and providing N latched write drivers in communication with the selected row.

4. The method of claim 1, wherein simultaneously transferring X, N/X-bit data portions between the selected row and the temporary storage comprises at least one of simultaneously reading all X, N/X-bit data portions from the selected row into the temporary storage and simultaneously writing all X, N/X-bit data portions from the temporary storage into the selected row.

5. A method for performing read and write operations in a burst-oriented semiconductor memory having a burst length of X, the method comprising:

selecting an N-bit wide row of the semiconductor memory,

providing N-bit wide temporary storage in communication with the selected row; and

simultaneously performing one of a read and a write transfer of X, N/X-bit data portions between the selected row and the temporary storage, where X comprises a nonzero positive integer.

6. A method for reading N data bits from a semiconductor memory, the method comprising:

selecting a row of the semiconductor memory in accordance with an externally supplied address;

simultaneously accessing N data bits stored in the selected row;

temporarily storing the simultaneously accessed N data bits;

selecting a portion of the temporarily stored N data bits in accordance with the externally supplied address;

reading out the portion of the temporarily stored N data bits selected in accordance with the externally supplied address;

generating one or more internal burst addresses from the externally supplied address; and

for each internal burst address generated, selecting a portion of the temporarily stored N data bits in accordance with the internal burst address and reading out the portion of the temporarily stored N data bits selected in accordance with the internal burst address.

7. The method of claim 6, wherein the semiconductor memory has a burst length of X, wherein the acts of selecting a portion of the temporarily stored N data bits comprises selecting N/X of the temporarily stored N data bits, where X comprises a nonzero positive integer.

8. The method of claim 6, wherein the semiconductor memory has a burst length of X, where X comprises a nonzero positive integer, wherein the act of generating one or more internal burst addresses comprises generating X−

1 internal burst addresses.

9. A method for reading N data bits from a burst-oriented Static Random Access Memory (SRAM) having a burst length of X, the method comprising:

selecting an N-bit-wide row of the SRAM in accordance with an externally supplied address;

simultaneously accessing N data bits in the selected row;

temporarily storing the simultaneously accessed N data bits;

selecting N/X data bits from the temporarily stored N data bits in accordance with the externally supplied address, where X comprises a nonzero positive integer;

reading out the N/X data bits selected in accordance with the externally supplied address;

generating X−

1 internal burst addresses from the externally supplied address; and

for each internal burst address generated,

selecting N/X data bits from the temporarily stored N data bits in accordance with the internal burst address; and

reading out the N/X data bits selected in accordance with the internal burst address.

10. A method for writing N data bits into a semiconductor memory, the method comprising:

receiving the N data bits in a plurality of sequential portions;

temporarily storing one of the sequential portions of the N data bits in accordance with an externally supplied address;

generating one or more internal burst addresses from the externally supplied address;

for each internal burst address generated, temporarily storing one of the sequential portions of the N data bits in accordance with the internal burst address;

selecting a row of the semiconductor memory in accordance with the externally supplied address; and

simultaneously writing the temporarily stored sequential portions of the N data bits into the selected row.

11. The method of claim 10, wherein the semiconductor memory has a burst length of X, where X comprises a nonzero positive integer, wherein the act of receiving the N data bits comprises receiving the N data bits in sequential, N/X-bit portions.

12. The method of claim 10, wherein the semiconductor memory has a burst length of X, where X comprises a nonzero positive integer, wherein the acts of temporarily storing one of the sequential portions of the N data bits comprises temporarily storing one of the sequential portions of the N data bits in N/X latched write drivers.

13. A method for writing N data bits into a burst-oriented Static Random Access Memory (SRAM) having a burst length of X, the method comprising:

receiving the N data bits in X sequential portions of N/X data bits each, where X comprises a nonzero positive integer;

temporarily storing one of the X sequential portions of N/X data bits in accordance with an externally supplied address;

generating X−

1 internal burst addresses from the externally supplied address;

for each internal burst address generated, temporarily storing one of the X sequential portions of N/X data bits in accordance with the internal burst address;

selecting an N-bit-wide row of the SRAM in accordance with the externally supplied address; and

simultaneously writing the temporarily stored X sequential portions of N/X data bits each into the selected row.

14. A burst-oriented Static Random Access Memory (SRAM) having a burst length of X, the SRAM comprising:

a memory array including a plurality of N-bit wide rows;

storage circuitry coupled to the memory array for temporarily storing N bits;

buffer circuitry for buffering X sequential data portions of N/X bits each, where X comprises a nonzero positive integer;

multiplexing circuitry coupled between the storage circuitry and the buffer circuitry for sequentially transferring the X sequential data portions between the storage circuitry and the buffer circuitry; and

circuitry coupled to the storage circuitry for directing the storage circuitry to simultaneously transfer N bits between a selected N-bit wide row of the memory array and the storage circuitry.

15. The SRAM of claim 14, wherein the memory array comprises a sub-array.

16. The SRAM of claim 14, wherein the storage circuitry comprises at least one of N latched sense amplifiers and N latched write drivers.

17. The SRAM of claim 14, wherein the buffer circuitry comprises at least one of input buffer circuitry and output buffer circuitry.

18. The SRAM of claim 14, wherein the multiplexing circuitry includes a plurality of multiplexors for transferring the X data portions in sequence in accordance with an externally generated address and X−

1 internally generated burst addresses.

19. The SRAM of claim 14, wherein the circuitry for directing the storage circuitry comprises a write controller.

20. The SRAM of claim 14, wherein the circuitry for directing the storage circuitry to simultaneously transfer N bits between a selected N-bit wide row of the memory array and the storage circuitry comprises circuitry for directing the storage circuitry to simultaneously write N bits from the storage circuitry into the selected N-bit wide row.

21. The SRAM of claim 14, wherein the circuitry for directing the storage circuitry to simultaneously transfer N bits between a selected N-bit wide row of the memory array and the storage circuitry comprises circuitry for directing the storage circuitry to simultaneously read N bits from the selected N-bit wide row into the storage circuitry.

22. A semiconductor memory comprising:

a memory array;

an address register for registering a plurality of externally supplied addresses;

burst control logic coupled to the memory array and the address register and externally supplied control signals for generating burst addresses from two or more least significant bits of the plurality of registered addresses;

data I/O circuitry coupled to said memory array for transmitting and receiving data;

a write controller coupled to said memory array and data I/O circuitry for generating read and write signals from said externally supplied control signals; and

data output enable circuitry coupled to said externally supplied control signals and said data I/O for generating an output enable signal.

23. The semiconductor memory of claim 22, wherein said memory array comprises a plurality of memory sub-array blocks.

24. The semiconductor memory of claim 23, wherein each of said plurality of memory sub-array blocks includes:

a sub-array;

a plurality of column pass circuitry blocks coupled to rows of said sub-array;

a plurality of latching sense amplifiers coupled to said plurality of column pass circuitry blocks for reading data from said sub-array;

a plurality of latched write drivers coupled to said plurality of column pass circuitry blocks for writing data into said sub-array;

I/O logic circuitry for communicating with an external data bus; and

a plurality of multiplexers coupled to outputs of said plurality of latching sense amplifiers and to inputs of said plurality of latched write drivers and to said I/O logic circuitry for controlling burst read and burst write addressing.

25. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a semiconductor memory comprising:

a memory array;

storage circuitry coupled to the memory array for temporarily storing N bits;

buffer circuitry for buffering X sequential data portions of N/X bits each, where X comprises a nonzero positive integer;

circuitry coupled between the storage circuitry and the buffer circuitry for sequentially transferring the X sequential data portions between the storage circuitry and the buffer circuitry; and

circuitry coupled to the storage circuitry for directing the storage circuitry to simultaneously transfer N bits between the memory array and the storage circuitry.

26. A semiconductor substrate having a semiconductor memory fabricated on a surface thereof, the semiconductor memory comprising:

a memory array;

storage circuitry coupled to the memory array for temporarily storing N bits;

buffer circuitry for buffering X sequential data portions of N/X bits each, where X comprises a nonzero positive integer;

circuitry coupled between the storage circuitry and the buffer circuitry for sequentially transferring the X sequential data portions between the storage circuitry and the buffer circuitry; and

circuitry coupled to the storage circuitry for directing the storage circuitry to simultaneously transfer N bits between the memory array and the storage circuitry.

27. The semiconductor substrate of claim 26, wherein the substrate comprises a semiconductor wafer.