Integrated circuit memory device having interleaved read and program capabilities and methods of operating same

• US 6,469,955 B1
• Filed: 11/21/2000
• Issued: 10/22/2002
• Est. Priority Date: 11/21/2000
• Status: Expired due to Term

• Current Assignee: Integrated Memory Technologies Incorporated
• Original Assignee: Integrated Memory Technologies Incorporated
• Inventors: Tsao, Cheng-Chung, Lin, Tien-ler
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/718,649
• Time in Patent Office: 700 Days
• Field of Search: 365/238.5, 365/185.17, 365/189.05, 365/230.08
• US Class Current: 365/238.5
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively. This sub-page programming technique greatly reduces the disturbance and programming time.

Claims

1. An integrated circuit memory device for emulating the read operation of a NAND memory device, said integrated circuit memory device comprising:

an array of floating gate memory cells arranged in a NOR configuration, and electrically coupled to a respective plurality of word lines and a plurality of bit lines;

said array arranged in a plurality of sub-pages of memory cells wherein each of said floating gate memory cells programmed by hot electron channel injection;

a plurality of sub-page buffers electrically coupled to said plurality of bit lines for storing data read from said memory cells coupled to said plurality of bit lines; and

a read control circuit coupled to said plurality of sub-page buffers for initiating a read operation to read data from a first sub-page of memory cells into a first sub-page buffer, and for initiating a read operation to read data from said first sub-page buffer to external to said integrated circuit memory device, while simultaneously for initiating a read operation to read data from a second sub-page of memory cells into a second sub-page buffer.

2. The device of claim 1 wherein each of said plurality of sub-pages of memory cells comprises a plurality of non-adjacent evenly spaced bit lines with memory cells coupled thereto, with said plurality of sub-pages of memory cells interleaving one another.

3. The device of claim 2 wherein each sub-page buffer is associated with a plurality of adjacent bit lines;

and

a column selection circuit for selecting a sub-page buffer to

one of said plurality of adjacent bit lines.

4. The device of claim 3 wherein each sub-page buffer is associated with two bit lines.

5. The device of claim 4 wherein each sub-page buffer further comprises:

a latch;

a reset circuit coupled to said latch; and

a switch for connecting to said latch to said column selection circuit.

6. An integrated circuit memory device for emulating the programming operation of a NAND memory device, said integrated circuit memory device comprising:

an array of floating gate memory cells arranged in a NOR configuration, and electrically coupled to a respective plurality of word lines and a plurality of bit lines;

said array arranged in a plurality of sub-pages of memory cells wherein each of said floating gate memory cells programmed by hot electron channel injection;

a plurality of sub-page buffers electrically coupled to said plurality of bit lines for storing data, externally supplied to said device, and to be programmed into said memory cells coupled to said plurality of bit lines; and

a programming control circuit coupled to said plurality of sub-page buffers for initiating a programming operation to program data sequentially from one sub-page buffer into an associated sub-page of memory cells until data from said plurality of sub-page buffers are programmed into said plurality of sub-page memory cells.

7. The device of claim 6, further comprising:

a read control circuit coupled to said plurality of sub-page buffers for initiating a read operation to read data from a first sub-page of memory cells into a first sub-page buffer, and for initiating a read operation to read data from said first sub-page buffer to external to said integrated circuit memory device, while simultaneously for initiating a read operation to read data from a second sub-page of memory cells into a second sub-page buffer.

8. The device of claim 6 wherein each of said plurality of sub-pages of memory cells comprises a plurality of non-adjacent evenly spaced bit lines with memory cells coupled thereto, with said plurality of sub-pages of memory cells interleaving one another.

9. The device of claim 8 wherein each sub-page buffer is associated with a plurality of adjacent bit lines;

and

a column selection circuit for selecting a sub-page buffer to one of said plurality of adjacent bit lines.

10. The device of claim 9 wherein each sub-page buffer is associated with two bit lines.

11. The device of claim 10 wherein each sub-page buffer further comprises:

a latch;

a reset circuit coupled to said latch; and

a switch for connecting to said latch to said column selection circuit.