Supervisory method for determining optimal process targets based on product performance in microelectronic fabrication

• US 6,470,230 B1
• Filed: 01/04/2000
• Issued: 10/22/2002
• Est. Priority Date: 01/04/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Toprac, Anthony J., Miller, Michael L., Sonderman, Thomas
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): Bahta, Kidest
• Application Number:
  US09/477,464
• Time in Patent Office: 1,022 Days
• Field of Search: 700/13, 700/108, 700/174, 700/109, 700/121, 700/222, 700/175, 700/182, 700/101, 700/91, 731/05, 438/8
• US Class Current: 700/121
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is provided. for manufacturing, the method including processing a workpiece in a processing step, measuring a parameter characteristic of the processing performed on the workpiece in the processing step, and forming an output signal corresponding to the characteristic parameter measured. The method also includes setting a target value for the processing performed in the processing step based on the output signal.

Claims

1. A method of manufacturing, the method comprising:

processing a workpiece in a processing step;

measuring a parameter characteristic of the processing performed on the workpiece in the processing step;

performing a parameter characteristic modeling process in response to the measuring the parameter characteristic;

forming an output signal based upon the parameter characteristic modeling process; and

setting a target value as a feedback for the processing performed in the processing step based on the output signal.

2. The method of claim 1, wherein measuring the characteristic parameter includes measuring a wafer electrical test (WET) parameter value of a transistor.

3. The method of claim 2, wherein forming the output signal corresponding to the characteristic parameter measured includes using the WET parameter value measured as an input to a transistor model.

4. The method of claim 3, wherein setting the target value for the processing performed in the processing step based on the output signal includes inverting the transistor model to define a change in the processing performed in the processing step needed to bring the WET parameter value measured within a range of specification values.

5. The method of claim 4, wherein inverting the transistor model to define the change in the processing performed in the processing step includes defining a change in a critical dimension of a feature formed in the processing step needed to bring the WET parameter value measured within the range of specification values.

6. The method of claim 5, wherein defining the change in the critical dimension of the feature formed in the processing step includes defining the change in the critical dimension of a poly gate line width of an MOS transistor.

7. The method of claim 5, wherein defining the change in the critical dimension of the feature formed in the processing step includes defining the change in the critical dimension of a junction depth of a source/drain region and a structure layer of an MOS transistor.

8. The method of claim 4, wherein inverting the transistor model to define the change in the processing performed in the processing step includes defining a change in a doping level of a feature formed in the processing step needed to bring the WET parameter value measured within the range of specification values.

9. The method of claim 8, wherein defining the change in the doping level of the feature formed in the processing step includes defining the change in the doping level of a source/drain region of an MOS transistor.

10. The method of claim 8, wherein defining the change in the doping level of the feature formed in the processing step includes defining the change in the doping level of a lightly doped drain (LDD) region of an MOS transistor.

11. A method of manufacturing, the method comprising:

processing a workpiece in first and second processing steps;

measuring parameters characteristic of the processing performed on the workpiece in the first and second processing steps;

performing a parameter characteristic modeling process in response to the measuring the parameter characteristic;

forming an output signal based upon the parameter characteristic modeling process; and

setting a target value for the processing performed in at least one of the first and second processing steps based on the output signal.

12. The method of claim 11, wherein measuring the characteristic parameters includes measuring at least one wafer electrical test (WET) parameter value of a transistor.

13. The method of claim 12, wherein forming the output signal corresponding to the characteristic parameters measured includes using the at least one WET parameter value measured as an input to a transistor model.

14. The method of claim 13, wherein setting the target value for the processing performed in the at least one of the first and second processing steps based on the output signal includes inverting the transistor model to define a change in the processing performed in the at least one of the first and second processing steps needed to bring the at least one WET parameter value measured within a range of specification values.

15. The method of claim 14, wherein inverting the transistor model to define the change in the processing performed in the at least one of the first and second processing steps includes defining a change in one of a critical dimension and a doping level of a feature formed in the at least one of the first and second processing steps needed to bring the at least one WET parameter value measured within the range of specification values.

16. A method of manufacturing, the method comprising:

processing a workpiece in a plurality of processing steps;

measuring parameters characteristic of the processing performed on the workpiece in the plurality of processing steps after the workpiece has been completely processed;

performing a parameter characteristic modeling process in response to the measuring the parameter characteristic;

forming an output signal based upon the parameter characteristic modeling process; and

setting a target value for the processing performed in at least one of the plurality of processing steps based on the output signal.

17. The method of claim 16, wherein measuring the characteristic parameters includes measuring wafer electrical test (WET) parameter values of a transistor.

18. The method of claim 17, wherein forming the output signal corresponding to the characteristic parameters measured includes using the WET parameter values measured as inputs to a transistor model.

19. The method of claim 18, wherein setting the target value for the processing performed in the processing step based on the output signal includes inverting the transistor model to define a change in the processing performed in the at least one of the plurality of processing steps needed to bring the WET parameter values measured within respective ranges of specification values.

20. The method of claim 19, wherein inverting the transistor model to define the change in the processing performed in the at least one of the plurality of processing steps includes defining a change in a critical dimension of a feature formed in the at least one of the plurality of processing steps needed to bring the WET parameter values measured within the respective ranges of specification values.

21. The method of claim 20, wherein defining the change in the critical dimension of the feature formed in the at least one of the plurality of processing steps includes defining the change in the critical dimension of a poly gate line width of an MOS transistor.

22. The method of claim 20, wherein defining the change in the critical dimension of the feature formed in the at least one of the plurality of processing steps includes defining the change in the critical dimension of a junction depth of a source/drain region and a structure layer of an MOS transistor.

23. The method of claim 19, wherein inverting the transistor model to define the change in the processing performed in the at least one of the plurality of processing steps includes defining a change in a doping level of a feature formed in the at least one of the plurality of processing steps needed to bring the WET parameter values measured within the respective ranges of specification values.

24. The method of claim 23, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a source/drain region of an MOS transistor.

25. The method of claim 23, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a lightly doped drain (LDD) region of an MOS transistor.

26. The method of claim 20, wherein inverting the transistor model to define the change in the processing performed in the at least one of the plurality of processing steps further includes defining a change in a doping level of a feature formed in the at least one of the plurality of processing steps needed to bring the WET parameter values measured within the respective ranges of specification values.

27. The method of claim 26, wherein defining the change in the critical dimension of the feature formed in the at least one of the plurality of processing steps includes defining the change in the critical dimension of a poly gate line width of an MOS transistor.

28. The method of claim 26, wherein defining the change in the critical dimension of the feature formed in the at least one of the plurality of processing steps includes defining the change in the critical dimension of a junction depth of a source/drain region and a structure layer of an MOS transistor.

29. The method of claim 26, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a source/drain region of an MOS transistor.

30. The method of claim 26, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a lightly doped drain (LDD) region of an MOS transistor.

31. The method of claim 27, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a source/drain region of an MOS transistor.

32. The method of claim 27, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a lightly doped drain (LDD) region of an MOS transistor.

33. The method of claim 28, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a source/drain region of an MOS transistor.

34. The method of claim 28, wherein defining the change in the doping level of the feature formed in the at least one of the plurality of processing steps includes defining the change in the doping level of a lightly doped drain (LDD) region of an MOS transistor.

35. A computer-readable, program storage device, encoded with instructions that, when executed by a computer, perform a method for manufacturing a workpiece, the method comprising:

processing a workpiece in a processing step;

measuring a parameter characteristic of the processing performed on the workpiece in the processing step;

performing a parameter characteristic modeling process in response to the measuring the parameter characteristic;

forming an output signal based upon the parameter characteristic modeling process; and

setting a target value for the processing performed in the processing step based on the output signal.

36. A computer programmed to perform a method of manufacturing, the method comprising:

processing a workpiece in a processing step;

measuring a parameter characteristic of the processing performed on the workpiece in the processing step;

performing a parameter characteristic modeling process in response to the measuring the parameter characteristic;

forming an output signal based upon the parameter characteristic modeling process; and

setting a target value for the processing performed in the processing step based on the output signal.

37. An apparatus, comprising:

means for processing a workpiece in a processing step;

means for measuring a parameter characteristic of the processing performed on the workpiece in the processing step;

means for performing a parameter characteristic modeling process in response to the measuring the parameter characteristic;

means for forming an output signal based upon the parameter characteristic modeling process; and

means for setting a target value as a feedback for the processing performed in the processing step based on the output signal.