Signal processing device accessible as memory

• US 6,470,380 B1
• Filed: 10/21/1997
• Issued: 10/22/2002
• Est. Priority Date: 12/17/1996
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshizawa, Hideki, Nomura, Yuji, Tsuruta, Toru, Kumamoto, Norichika
• Primary Examiner(s): Maung, Zarni
• Assistant Examiner(s): CALDWELL, ANDREW T
• Application Number:
  US08/955,089
• Time in Patent Office: 1,827 Days
• Field of Search: 712/28-31, 712/35, 709/213-216, 711/152, 711/147, 711/150, 711/151
• US Class Current: 709/213
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451

Abstract

A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Claims

1. A device for signal processing connected to an external bus, comprising:

information processing units; and

communication links connected between said information processing units, wherein each of said information processing units comprises;

a signal processing unit processing data;

a first storage unit storing data and programs executed by said signal processing unit, said first storage unit directly connected to the external bus without any intervening elements therebetween and functioning as a memory for a host device connected to the external bus;

a second storage unit which functions as a work area for said signal processing unit, said second storage unit being separate from said first storage unit and not connected to the external bus; and

a communication control unit communicating data with at least one other information processing unit via at least one of the communication links and connected to the first and the second storage units, the communication control unit comprising a first cache memory of the signal processing unit that stores the data received from the first storage unit and the data received via the communication links and a second cache memory of the signal processing unit that stores the data received via the communication links and used to exchange data with the other information processing units via the communication links.

2. The device as claimed in claim 1, wherein said information processing units are connected in series via said communication links.

3. The device as claimed in claim 2, wherein said first storage unit comprises:

a memory storing said data and said programs;

a memory control unit in communication with the memory and controlling said memory so that said memory is accessible by the host device using said external bus to write and read said data in and from the first storage unit.

4. The device as claimed in claim 3, wherein said memory control unit comprises a key-data storage unit for storing key information, and controls said memory so that said memory is accessible from said external bus only when data matching said key information is provided from said external bus.

5. The device as claimed in claim 2, wherein said information processing units process data in parallel.

6. The device as claimed in claim 2, wherein said information processing units process data through a pipe-line operation by successively passing data from one of said information processing units to another one of said information processing units via said communication links.

8. The device as claimed in claim 1, wherein said information processing units are connected in series via said communication links.

9. A device as claimed in claim 8, wherein said first storage unit comprises:

a memory storing said data and said programs;

a memory control unit in communication with the memory and controlling said memory so that said memory is accessible by the host device using said shared bus to write and read said data in and from the first storage unit.

10. The device as claimed in claim 9, wherein said memory control unit comprises a key-data storage unit for storing key information, and controls said memory so that said memory is accessible from said shared bus only when data matching said key information is provided from said shared bus.

11. The device as claimed in claim 8, wherein said information processing units process data in parallel.

12. The device as claimed in claim 8, wherein said information processing units process data through a pipe-line operation by successively passing data from one of said information processing units to another one of said information processing units via said communication links.

13. The device as claimed in claim 8, further comprising a CPU which controls said information processing units via said shared bus and conducts data processing, wherein said information processing units execute an instruction when said instruction fetched by said CPU causes an instruction exception.

7. A device for signal processing, comprising:

information processing units;

communication links connected between said information processing units; and

a shared bus connected to each of said information processing units, wherein each of said information processing units comprises;

a signal processing unit processing data;

a first storage unit storing data and programs executed by said signal processing unit, said first storage unit directly connected to the shared bus without any intervening elements therebetween and functioning as a memory for a host device connected to the shared bus;

a second storage unit which functions as a work area for said signal processing unit, said second storage unit being separate from said first storage unit and not connected to the shared bus; and

a communication control unit communicating data with at least one other information processing unit via at least one of the communication links and connected to the first and the second storage units, the communication control unit comprising a first cache memory of the signal processing unit that stores the data received from the first storage unit and the data received via the communication links and a second cache memory of the signal processing unit that stores the data received via the communication links and used to exchange data with the other information processing units via the communication links.