Interface for a data node of a data network

• US 6,470,393 B1
• Filed: 03/04/1999
• Issued: 10/22/2002
• Est. Priority Date: 03/06/1998
• Status: Expired due to Term

• Current Assignee: Bayerische Motoren Werke AG, STMicroelectronics GmbH (STMicroelectronics NV)
• Original Assignee: BMW AG (Bayerische Motoren Werke AG), STMicroelectronics GmbH (STMicroelectronics NV)
• Inventors: Kuhls, Burkhard, Heinrich, Peter
• Primary Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US09/262,499
• Time in Patent Office: 1,328 Days
• Field of Search: 709/244, 709/238, 370/292, 370/351, 711/202
• US Class Current: 709/238
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/40039 Details regarding the setting of the power status of a node according to activity on the bus
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An interface for a data node of a data network including a plurality of data nodes are connected to each other by way of a bus line and activatable in selective manner by address codes transmitted via the bus line. The interface includes an activating address filter allowing addresses intended for the associated data node to be recognized.

Claims

1. A data node for a data network comprising a plurality of data nodes interconnected by means of a bus line and selectively activatable by address codes transmitted via the bus line,

wherein the data node comprises:

a microcontroller switchable between inactive and active operation modes;

an interface interconnected between the bus line and the microcontroller; and

an address filter configured to recognize an activating demand intended for the microcontroller to initiate switching of the microcontroller from the inactive to the active operation modes, the address filter located in the interface.

2. The data node of claim 1,

comprising an address shift register for temporarily storing an address bit sequence received via the bus line,

a filter register for permanently storing an address bit sequence corresponding to the address of the data node considered,

and a comparison means for comparing the respective address bit sequence stored in the address shift register with respect to conformity with the address bit sequence stored in the filter register,

the comparison means generating a comparison result signal which is in the form of a wake-up signal when it ascertains conformity between the temporarily stored address bit sequence and the permanently stored address bit sequence.

3. The data node of claim 2, the interface,

comprising a mask by means of which, with respect to predetermined address bit locations, conformity between temporarily stored address bit sequence and permanently stored address bit sequence can be signaled irrespective of whether or not there is actually conformity for such an address bit location.

4. The data node of claim 2,

wherein the comparison result signal of the comparison means can be released only upon receipt of a release signal,

and comprising a bit counter adapted to count the bit locations of the respective bit sequence received and delivering a release signal to the comparison means upon reaching a predetermined bit count.

5. The data node of claim 2,

wherein the output of the comparison means has an OR element connected downstream thereof which subjects an output signal of the comparison means to an OR operation with an external wake-up signal and/or a priority wake up-signal.

6. The data node of claim 1,

comprising a bit clock recovering means for recovering the bit clock of the bit sequences received via the bus line.

7. The data node of claim 6 for a data network,

wherein bit sequences are sent in the form of frames via the bus line and each frame starts with a characteristic frame start bit followed by the address bits and thereafter by data bits:

comprising a differentiating member differentiating the pulse edges of the respective bit sequence as differentiating pulses of first and second polarity, respectively;

a bit length counter to which counting clock pulses of a counting clock oscillator can be supplied as pulses to be counted, to which the differentiating pulses of one polarity can be fed as counting start signals and the differentiating pulses of the other polarity as counter resetting signals, which at each resetting operation issues a bit change signal representing the recovered bit clock, and which is adapted to be reset at the beginning of a received frame start bit;

and a bit length memory the memory contents of which can be cleared at the respective frame start and in which, at the end of the respective frame start bit,

the then reached Count of the bit length counter can be stored;

the Count of the bit length counter being continuously compared to the bit length memory value and the bit length counter being reset each time it reaches the bit length memory value.

8. The data node of claim 7,

comprising a frame start recognition means by means of which the frame start of the respective bit sequence transmitted is recognizable and by means of which, at the frame beginning of a bit sequence, the bit length counter is adapted to be reset and the bit length memory is adapted to be cleared.

9. The data node of claim 8,

for a data network according to the protocol of which not more than a prescribed number of successive equal bit logic values may occur within a frame of a transmitted bit sequence,

wherein the frame start recognition means is fed with the bit clock pulses available at the output of the bit length counter and with the received bit sequence.

10. The data node of claim 1,

comprising an oscillator of moderate frequency accuracy which is tunable by means of characteristic quantities of received bit sequences and determines the clock control of a data processing means belonging to the interface.

11. The data node of claim 10, for a data network in which bit sequences are sent in the form of frames via the bus line and each frame starts with a characteristic frame start bit followed by address bits and thereafter by data bits,

comprising a controllable oscillator,

a frame actual length counter having a counting clock input,

a frame nominal length presetting means,

a comparison means comparing frame actual length and frame nominal length with each other,

and a summing means by means of which the Output signal of the comparison means can be added to a frequency setting value presetting a nominal frequency of the oscillator,

an output of the summing means being coupled with the control input of the oscillator and an oscillator output being coupled with the counting clock input of the frame actual length counter.

12. The data node of claim 11,

comprising a release-dependent temporary memory disposed between the comparison means and the summing means and having a release input which, when a release signal is applied thereto, releases a transfer of the temporarily stored comparison result to the summing means,

and a bit counter by means of which the number of bits occurring as from the frame start bit of a bit sequence can be counted and which, upon reaching a predetermined count, delivers a release signal to the temporary memory.

13. The data node of claim 11,

wherein a frequency divider is connected between the oscillator output and the counting clock input of the frame actual length counter.

14. The data node of claim 1 comprising:

a power supply; and

a voltage controller, the voltage controller connected to the power supply to received power and connected to to the microcontroller to supply power when the address filter of the interface has recognized an activating demand for the microcontroller.

15. The data node of claim 14 wherein the data network has a bus line comprising a data bus and a voltage supply line;

and wherein the interface couples the voltage controller with the voltage supply line when the address filter of the interface has recognized an activating demand for the microcontroller.

16. A data node of a data network having a plurality of data nodes interconnected by means of a bus line via which bit sequences can be transmitted, the data node comprising:

a microcontroller having quiescent and active states; and

a bit clock recovering means for recovering the bit clock of bit sequences received by the data node via the bus line without need for the microcontroller to be in its active state.

17. The data node of claim 16,

comprising a frame start recognition means by means of which the frame start of the respective bit sequence transmitted is recognizable and by means of which, at the frame beginning of a bit sequence, the bit length counter is adapted to be reset and the bit length memory is adapted to be cleared.

18. The data node of claim 17,

for a data network according to the protocol of which not more than a prescribed number of successive equal bit logic values may occur within a frame of a transmitted bit sequence,

wherein the frame start recognition means is fed on the one hand with the bit clock pulses available at the output of the bit length counter and on the other hand with the received bit sequence.

19. The data node of claim 16,

comprising an oscillator of moderate frequency accuracy which is tunable by means of characteristic quantities of received bit sequences and determines the clock control of a data processing means belonging to the interface.

20. The data node of claim 19, for a data network in which bit sequences are sent in the form of frames via the bus line and each frame starts with a characteristic frame start bit followed by address bits and thereafter by data bits,

comprising a controllable oscillator,

a frame actual length counter having a counting clock input,

a frame nominal length presetting means,

a comparison means comparing frame actual length and frame nominal length with each other,

and a summing means by means of which the output signal of the comparison means can be added to a frequency setting value presetting a nominal frequency of the oscillator,

an output of the summing means being coupled with the control input of the oscillator and an oscillator output being coupled with the counting clock input of the frame actual length counter.

21. The data node of claim 20,

comprising a release-dependent temporary memory disposed between the comparison means and the summing means and having a release input which, when a release signal is applied thereto, releases a transfer of the temporarily stored comparison result to the summing means,

and a bit counter by means of which the number of bits occurring as from the frame start bit of a bit sequence can be counted and which, upon reaching a predetermined count, delivers a release signal to the temporary memory.

22. The data node of claim 20,

wherein a frequency divider is connected between the oscillator output and the counting clock input of the frame actual length counter.

23. The data node of claim 20,

comprising a release-dependent temporary memory disposed between the comparison means and the summing means and having a release input which, when a release signal is applied thereto, releases a transfer of the temporarily stored comparison result to the summing means,

and a bit counter by means of which the number of bits occurring as from the frame start bit of a bit sequence can be counted and which, upon reaching a predetermined count, delivers a release signal to the temporary memory.

24. The data node of claim 20,

wherein a frequency divider is connected between the oscillator output and the counting clock input of the frame actual length counter.

25. The data node of claim 16 for a data network,

wherein bit sequences are sent in the form of frames via the bus line and each frame starts with a characteristic frame start bit followed by the address bits and thereafter by data bits;

comprising a differentiating member differentiating the pulse edges of the respective bit sequence as differentiating pulses of first and second polarity, respectively;

a bit length counter to which counting clock pulses of a counting clock oscillator can be supplied as pulses to be counted, to which the differentiating pulses of one polarity can be fed as counting start signals and the differentiating pulses of the other polarity as counter resetting signals, which at each resetting operation issues a bit change signal representing the recovered bit clock, and which is adapted to be reset at the beginning of a received frame start bit;

and a bit length memory the memory contents of which can be cleared at the respective frame start and in which, at the end of the respective frame start bit, the then reached count of the bit length counter can be stored;

the count of the bit length counter being continuously compared to the bit length memory value and the bit length counter being reset each time it reaches the bit length memory value.

26. A data node of a data network having a plurality of data nodes interconnected by means of a bus line via which bit sequences can be transmitted, the data node comprising:

a microcontroller having quiescent and active states; and

an interface having an oscillator of moderate frequency accuracy which is tunable by means of characteristic quantities of received bit sequences and determines the clock control of a data processing means belonging to the interface without need for the microcontroller to be in its active state.

27. The data node of claim 26, for a data network in which bit sequences are sent in the form of frames via the bus line and each frame starts with a characteristic frame start bit followed by address bits and thereafter by data bits,

comprising a controllable oscillator,

a frame actual length counter having a counting clock input,

a frame nominal length presetting means,

a comparison means comparing frame actual length and frame nominal length with each other,

and a summing means by means of which the output signal of the comparison means can be added to a frequency setting value presetting a nominal frequency of the oscillator,

an output of the summing means being coupled with the control input of the oscillator and an oscillator output being coupled with the counting clock input of the frame actual length counter.

28. A data network comprising a plurality of data nodes interconnected by means of a bus line and selectively activatable by address codes transmitted via the bus line,

each data node comprising:

a microcontroller switchable between inactive and active operation modes;

an interface interconnected between the bus line and the microcontroller; and

an address filter configured to recognize an activating demand intended for the microcontroller to initiate switching of the microcontroller from the inactive to the active operation modes, the address filter located in the interface.

29. The data network of claim 28,

wherein each interface comprises a bit clock recovering means for recovering the bit clock of the bit sequences received via the bus line.

30. The data network of claim 28,

wherein each interface comprises an oscillator of moderate frequency accuracy which is tunable by means of characteristic quantities of received bit sequences and determines the clock control of a data processing means belonging to the interface.

31. The data node of claim 28 comprising a power supply;

and

a voltage controller, the voltage controller connected to the power supply to received power and connected to the microcontroller belonging to an intended data node to supply power when the address filter of the interface belonging to the intended data node has recognized an activating demand for said microcontroller.

32. The data node of claim 31 wherein the data network has a bus line comprising a data bus and a voltage supply line;

and wherein the interface couples the voltage controller with the voltage supply line when the address filter of the interface belonging to the intended data node has recognized an activating demand for the microcontroller belonging to the intended data node.

33. A data network comprising a plurality of data nodes interconnected by a bus line via which bit sequences can be transmitted,

each data node having a microcontroller and an interface, the microcontroller having quiescent and active states, the interface comprising a bit clock recovering circuit for recovering the bit clock of the bit sequences received via the bus line without need for the microcontroller to be in its active state.

34. A data network comprising a plurality of data nodes interconnected by means of a bus line via which bit sequences can be transmitted,

each data node having a microcontroller and an interface, the microcontroller having quiescent and active states, the interface comprising an oscillator of moderate frequency accuracy which is tunable by means of characteristic quantities of received bit sequences and determines the clock control of a data processing means belonging to the interface without need for the microcontroller to be in its active state.