Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data

• US 6,470,431 B2
• Filed: 01/31/2001
• Issued: 10/22/2002
• Est. Priority Date: 01/31/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Kumar, Promod, Campanale, Fabrizio, Tomaiuolo, Francesco, De Ambroggi, Luca Giuseppe, Nicosia, Salvatore
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US09/774,542
• Publication Number:
  US 20010034819A1
• Time in Patent Office: 629 Days
• Field of Search: 711/5, 711/157, 365/230.02, 365/230.03, 365/230.04
• US Class Current: 711/157
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Claims

1. An interleaved memory having an interleaved data path and comprising:

an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells;

first and second arrays of sense amplifiers respectively coupled to said first and second banks of memory cells;

first and second read registers respectively coupled to said first and second arrays of sense amplifiers;

an array of output buffers;

a control and timing circuit connected to said first and second arrays of sense amplifiers, and having inputs for receiving externally generated command signals and outputs for providing path selection signals and a control signal;

a third register connected to said first and second read registers and having inputs for receiving read data therefrom as a function of the path selection signals; and

an array of pass-gates connected to said third register and being controlled in common by the control signal for enabling a transfer of the read data stored in said third register to said array of output buffers.

2. An interleaved memory according to claim 1, wherein said control and timing circuit comprises:

a pulse generator circuit for generating a primary loading pulse for loading the read data into said third register;

a first circuit for controlling generation of the primary loading pulse during a random access asynchronous read cycle and having inputs for receiving a plurality of command signals for the transfer of the read data to said third register; and

a second circuit for controlling sequential access synchronous read cycles and having a first input for receiving at least one of the plurality of command signals and a second input for receiving the primary loading pulse.

3. An interleaved memory according to claim 2, wherein said control and timing circuit further comprises a multiplexer having a first input for receiving an external timing signal, a second input for receiving an output signal from said first circuit and a selection input for receiving an output signal from said second circuit for selecting the first input during the sequential access synchronous read cycles, and an output connected to said pulse generator circuit.

4. An interleaved memory according to claim 2, wherein the plurality of command signals includes an address latch enabling signal, a confirmation signal for equalization of said first and second arrays of sense amplifiers, an increment pulse for internal address counters and at least one of the path enabling signals.

5. An interleaved memory according to claim 2, wherein said control and timing circuit further comprises a modulation circuit for modulating duration of the primary loading pulse during the random access asynchronous read cycle to correspond to duration of a primary enabling pulse for enabling transfer of the read data in one of said first and second read registers.

6. An interleaved memory according to claim 5, wherein said modulation circuit comprises an AND gate having a first inverting input for receiving the primary enabling pulse and a second input for receiving the output signal from said second circuit.

7. An interleaved memory according to claim 3, further comprising a pass-gate connected between the output of said multiplexer and an input of said pulse generator circuit for providing the primary loading pulse, said pass-gate having a control input connected to an output of said pulse generator circuit.

8. An interleaved memory according to claim 1, wherein said control and timing circuitry further comprises a secondary control circuit for generating secondary loading pulses for the read data in said first and second read registers based upon at least a primary loading pulse and a priority flag selecting one of said first and second banks of memory cells, and for generating the control signal for enabling data paths to respective inputs of said array of output buffers in synchronization with the secondary loading pulse which are in synchronization with the externally generated command signals for a sequential access synchronous read mode or a random access asynchronous read mode of the interleaved memory.

9. An interleaved memory according to claim 1, wherein the interleaved memory is readable in a sequential access synchronous read mode and in a random access asynchronous read mode.

10. An interleaved memory having an interleaved data path and comprising:

an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells;

first and second arrays of sense amplifiers respectively coupled to said first and second banks of memory cells;

first and second read registers respectively coupled to said first and second arrays of sense amplifiers;

an array of output buffers;

a control and timing circuit connected to said first and second arrays of sense amplifiers, and having inputs for receiving externally generated command signals and outputs for providing path selection signals and a control signal; and

a third register connected to said first and second read registers and having inputs for receiving read data therefrom as a function of the path selection signals;

said control and timing circuit comprising

a pulse generator circuit for generating a primary loading pulse for loading the read data into said third register,

a first circuit for controlling generation of the primary loading pulse during a random access asynchronous read cycle and having inputs for receiving a plurality of command signals for the transfer of the read data to said third register, and

a second circuit for controlling sequential access synchronous read cycles and having a first input for receiving at least one of the plurality of command signals and a second input for receiving the primary loading pulse.

11. An interleaved memory according to claim 10, further comprising an array of pass-gates connected to said third register and being controlled in common by the control signal for enabling a transfer of the read data stored in said third register to said array of output buffers.

12. An interleaved memory according to claim 10, wherein said control and timing circuit further comprises a multiplexer having a first input for receiving an external timing signal, a second input for receiving an output signal from said first circuit and a selection input for receiving an output signal from said second circuit for selecting the first input during the sequential access synchronous read cycles, and an output connected to said pulse generator circuit.

13. An interleaved memory according to claim 10, wherein the plurality of command signals includes an address latch enabling signal, a confirmation signal for equalization of said first and second arrays of sense amplifiers, an increment pulse for internal address counters and at least one of the path enabling signals.

14. An interleaved memory according to claim 10, wherein said control and timing circuit further comprises a modulation circuit for modulating duration of the primary loading pulse during the random access asynchronous read cycle to correspond to duration of a primary enabling pulse for enabling transfer of the read data in one of said first and second read registers.

15. An interleaved memory according to claim 14, wherein said modulation circuit comprises an AND gate having a first inverting input for receiving the primary enabling pulse and a second input for receiving the output signal from said second circuit.

16. An interleaved memory according to claim 12, further comprising a pass-gate connected between the output of said multiplexer and an input of said pulse generator circuit for providing the primary loading pulse, said pass-gate having a control input connected to an output of said pulse generator circuit.

17. An interleaved memory according to claim 10, wherein said control and timing circuitry further comprises a secondary control circuit for generating secondary loading pulses for the read data in said first and second read registers based upon at least a primary loading pulse and a priority flag selecting one of said first and second banks of memory cells, and for generating the control signal for enabling data paths to respective inputs of said array of output buffers in synchronization with the secondary loading pulse which are in synchronization with the externally generated command signals for a sequential access synchronous read mode or a random access asynchronous read mode of the interleaved memory.

18. An interleaved memory according to claim 10, wherein the interleaved memory is readable in a sequential access synchronous read mode and in a random access asynchronous read mode.

19. A circuit for providing an interleaved data path for an interleaved memory comprising an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second banks of memory cells, first and second read registers respectively coupled to the first and second arrays of sense amplifiers, and an array of output buffers, the circuit comprising:

a control and timing circuit connected to the first and second arrays of sense amplifiers, and having inputs for receiving externally generated command signals and outputs for providing path selection signals and a control signal;

a third register connected to the first and second read registers and having inputs for receiving data therefrom as a function of the path selection signals; and

an array of pass-gates connected to said third register and being controlled in common by the control signal for enabling a transfer of the read data stored in said third register to the array of output buffers.

20. A circuit according to claim 19, wherein said control and timing circuit comprises:

a pulse generator circuit for generating a primary loading pulse for loading the read data into said third register;

a first circuit for controlling generation of the primary loading pulse during a random access asynchronous read cycle and having inputs for receiving a plurality of command signals for the transfer of the read data to said third register; and

a second circuit for controlling sequential access synchronous read cycles and having a first input for receiving at least one of the plurality of command signals and a second input for receiving the primary loading pulse.

21. A circuit according to claim 20, wherein said control and timing circuit further comprises a multiplexer having a first input for receiving an external timing signal, a second input for receiving an output signal from said first circuit and a selection input for receiving an output signal from said second circuit for selecting the first input during the sequential access synchronous read cycles, and an output connected to said pulse generator circuit.

22. A circuit according to claim 20, wherein the plurality of command signals includes an address latch enabling signal, a confirmation signal for equalization of said first and second arrays of sense amplifiers, an increment pulse for internal address counters and at least one of the path enabling signals.

23. A circuit according to claim 20, wherein said control and timing circuit further comprises a modulation circuit for modulating duration of the primary loading pulse during the random access asynchronous read cycle to correspond to duration of a primary enabling pulse for enabling transfer of the read data in one of the first and second read registers.

24. A circuit according to claim 23, wherein said modulation circuit comprises an AND gate having a first inverting input for receiving the primary enabling pulse and a second input for receiving the output signal from said second circuit.

25. A circuit according to claim 21, further comprising a pass-gate connected between the output of said multiplexer and an input of said pulse generator circuit for providing the primary loading pulse, said pass-gate having a control input connected to an output of said pulse generator circuit.

26. A circuit according to claim 19, wherein said control and timing circuitry further comprises a secondary control circuit for generating secondary loading pulses for the read data in the first and second read registers based upon at least a primary loading pulse and a priority flag selecting one of the first and second banks of memory cells, and for generating the control signal for enabling data paths to respective inputs of the array of output buffers in synchronization with the secondary loading pulse which are in synchronization with the externally generated command signals for a sequential access synchronous read mode or a random access asynchronous read mode of the interleaved memory.

27. A circuit according to claim 19, wherein the interleaved memory is readable in a sequential access synchronous read mode and in a random access asynchronous read mode.

28. A method for providing an interleaved data path in an interleaved memory comprising an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second banks of memory cells, first and second read registers respectively coupled to the first and second arrays of sense amplifiers, and an array of output buffers, the method comprising:

providing externally generated command signals to a control and timing circuit for generating path selection signals and a control signal;

transferring read data from the first and second read registers to a third register as a function of the path selection signals; and

controlling in common an array of pass-gates connected to the third register for enabling a transfer of the read data stored in the third register to the array of output buffers.

29. A method according to claim 28, further comprising:

generating a primary loading pulse for loading the read data into the third register;

controlling generation of the primary loading pulse using a first circuit during a random access asynchronous read cycle, the first circuit having inputs for receiving a plurality of command signals for the transfer of the read data to the third register; and

controlling sequential access synchronous read cycles using a second circuit having a first input for receiving at least one of the plurality of command signals and a second input for receiving the primary loading pulse.

30. A method according to claim 29, further comprising multiplexing an external timing signal, an output signal from the first circuit and an output signal from the second circuit for selecting the external timing signal during the sequential access synchronous read cycles.

31. A method according to claim 29, wherein the plurality of command signals includes an address latch enabling signal, a confirmation signal for equalization of the first and second arrays of sense amplifiers, an increment pulse for internal address counters and at least one of the path enabling signals.

32. A method according to claim 29, further comprising modulating duration of the primary loading pulse during the random access asynchronous read cycle to correspond to duration of a primary enabling pulse for enabling transfer of the read data in one of said first and second read registers.

33. A method according to claim 28, further comprising:

generating secondary loading pulses for the read data in the first and second read registers based upon at least a primary loading pulse and a priority flag selecting one of the first and second banks of memory cells; and

generating the control signal for enabling data paths to respective inputs of the array of output buffers in synchronization with the secondary loading pulse which are in synchronization with the externally generated command signals for a sequential access synchronous read mode or a random access asynchronous read mode of the interleaved memory.

34. A method according to claim 28, wherein the interleaved memory is readable in a sequential access synchronous read mode and in a random access asynchronous read mode.