Processor assigning data to hardware partition based on selectable hash of data address

• US 6,470,442 B1
• Filed: 07/30/1999
• Issued: 10/22/2002
• Est. Priority Date: 07/30/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Clark, Leo James, Arimilli, Ravi Kumar, Guthrie, Guy Lynn, Lewis, Jerry Don, Dodson, John Steve
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/364,286
• Time in Patent Office: 1,180 Days
• Field of Search: 711/129, 711/153, 711/173, 712/32, 709/104
• US Class Current: 712/32
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.

Claims

1. A processor, comprising:

execution resources;

data storage; and

an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources;

wherein at least one of said execution resources and said instruction sequencing unit is implemented with a plurality of hardware partitions of like function, and wherein said processor selectively assigns data for processing by particular ones of said plurality of hardware partitions according to a selectable hash of addresses associated with said data.

2. The processor of claim 1, wherein said processor alters said selectable hash in response to detection of an error.

3. The processor of claim 1, wherein said processor alters said selectable hash dynamically during operation.

4. The processor of claim 1, wherein said processor alters said selectable hash in response to detection of a load imbalance between said plurality of hardware partitions.

5. The processor of claim 1, said instruction sequencing unit including a hash selection circuit that selects among a plurality of possible hashes and implements a selected one of said plurality of hashes.

6. The processor of claim 1, wherein said data storage and said execution resources are implemented with a same number of hardware partitions.

7. The processor of claim 1, wherein said instruction sequencing unit is implemented with a plurality of hardware partitions of like function.

8. A data processing system, comprising:

at least one interconnect;

at least one memory coupled to said interconnect; and

at least one processor coupled to said interconnect, wherein said processing includes;

execution resources;

data storage; and

an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources;

wherein at least one of said execution resources and said instruction sequencing unit is implemented with a plurality of hardware partitions of like function, and wherein said processor selectively assigns data for processing by particular ones of said plurality of hardware partitions according to a selectable hash of addresses associated with said data.

9. The data processing system of claim 8 wherein said processor alters said selectable hash in response to detection of an error.

10. The data processing system of claim 8, wherein said processor alters said selectable hash dynamically during operation.

11. The data processing system of claim 8, wherein said processor alters said selectable hash in response to detection of a load imbalance between said plurality of hardware partitions.

12. The data processing system of claim 8, said instruction sequencing unit including a hash selection circuit that selects among a plurality of possible hashes and implements a selected one of said plurality of hashes.

13. The data processing system of claim 8, wherein said data storage and said execution resources are implemented with a same number of hardware partitions.

14. The data processing system of claim 8, wherein said instruction sequencing unit is implemented with a plurality of hardware partitions of like function.

15. A method of operating a processor, including execution resources, data storage, and an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources, said method comprising:

processing data within a plurality of hardware partitions of like function, wherein at least one of said execution resources and said instruction sequencing unit is implemented with said plurality of hardware partitions, and wherein said data are assigned for processing by particular ones of said plurality of hardware partitions according to a selectable hash of addresses associated with said data; and

reassigning at least some of said data to others of said plurality of hardware partitions by altering said selectable hash.

16. The method of claim 15, wherein reassigning at least some of said data comprises altering said selectable hash in response to detection of an error.

17. The method of claim 15, wherein reassigning at least some of said data comprises altering said selectable hash dynamically during operation of said processor.

18. The method of claim 15, where assigning at least some of said data comprises altering said selectable hash in response to detection of a load imbalance between said plurality of hardware partitions.

19. The method of claim 15, where in said instruction sequencing unit includes hash selection circuit having a plurality of diverse hashes, and wherein reassigning at least some of said data comprises selecting a different one of said plurality of diverse hashes.

20. The method of claim 15, wherein processing data within a plurality of hardware partitions of like function comprises processing said data within a corresponding plurality of hardware partitions in said data storage and within a corresponding plurality of hardware partitions in said execution resources.