METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION

• US 6,470,482 B1
• Filed: 08/05/1996
• Issued: 10/22/2002
• Est. Priority Date: 04/06/1990
• Status: Expired due to Fees

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dangelo, Carlos, Watkins, Daniel R., Rostoker, Michael D.
• Primary Examiner(s): JONES, HUGH M
• Application Number:
  US08/689,204
• Time in Patent Office: 2,269 Days
• Field of Search: 716/6, 716/5, 716/2
• US Class Current: 716/102
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G01R 31/318378 of patterns for devices arranged in a network
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations. Schematic diagram and simulation displays showing those portions of the electronic system and simulated signal patterns which are related to the design rule violations are used to help the user identify and appropriately correct problems in the design.

Claims

1. In an ECAD system, a method of creating and validating a structural description of an electronic system from a higher level, behavior-oriented description thereof, comprising:

entering on an ECAD system a specification for a design of desired behavior of an electronic system, including timing goals, in a high-level, behavior-oriented language;

simulating and changing the design of the electronic system at the behavioral level until the desired behavior is obtained;

displaying the design of at least a portion of the electronic system as a plurality of graphical objects forming a schematic diagram and simultaneously displaying simulation data on the schematic diagram adjacent to graphical objects to which the simulation data applies;

partitioning the design of the device into a number of architectural blocks and constraining the architectural choices to those which meet the timing goals; and

directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a netlist or gate-level description of the design.

2. A method according to claim 1, wherein:

architectural blocks having highly regular structures or well understood functions are directed to specific logic synthesis programs running on the ECAD system (e.g. memory or function compilers); and

architectural blocks with random or unstructured logic are directed to more general logic synthesis programs running on the ECAD system.

3. A method according to claim 1, further comprising:

on the ECAD system, simulating the gate-level design description; and

on the ECAD system, comparing the results of the gate-level simulation with those from the behavioral simulation to ensure that the gate-level design description behaves as intended and that the timing goals are achieved.

4. A method according to claim 3, further comprising:

on the ECAD system, back-annotating the design to ensure that other physical design limitations, such as capacitive loads, are not exceeded.

5. A method according to claim 3, further comprising:

inputting to the ECAD system the net list or gate-level description of the design to a layout tool running on the ECAD system for creating a physical implementation of the design.

6. A method according to claim 1, wherein:

the high-level behavioral description of the device is set forth in VHDL.

7. A method according to claim 1, further comprising:

interpreting the behavioral description of the device by attaching one or more semantic rules to each of the syntactic rules underlying the behavioral description, in the ECAD system.

8. A method according to claim 1, further comprising:

identifying, in the description of the electronic system, violations of pre-determined design rules;

providing indications of the design rule violations and information about the nature of the violations and the conditions under which they occur; and

displaying schematic objects and simulations results corresponding to the design rule violations on a schematic representation of at least a portion of the design.

9. A method according to claim 8, further comprising:

providing an expert system;

providing the indications of and information about the design rule violations to the expert system;

forming, by means of the expert system, suggestions for alterations to the design which correct or eliminate the design rule violation; and

displaying the suggested design alterations.

10. In an ECAD system, a method of creating and validating a structural description of an electronic system from a behavior-oriented description, comprising:

specifying a behavioral description for a design of desired behavior of an electronic system in a high-level, behavior-oriented language, and inputting the behavioral description to an ECAD system;

iteratively simulating and changing the behavioral description until the desired behavior is obtained;

partitioning the behavioral description into architectural blocks;

analyzing the specification for syntactic and semantic correctness;

forming a parse tree from the specification. wherein each node of the parse tree is associated with semantic rules; and

constructing hierarchical knowledge bases from the semantic rules, wherein the semantic rules are used to construct a knowledge base for each block of the specification and to derive hierarchical relationships among the knowledge bases, and the hierarchical knowledge bases comprise a structural description of the specification.

11. A method according to claim 10, wherein:

the electronic system is a design entity; and

the design entity is an entire system, a sub-system, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between.

12. A method according to claim 10, further comprising:

identifying, in the description of the electronic system, violations of pre-determined design rules;

providing indications of the design rule violations and information about the nature of the violations and the conditions under which they occur; and

displaying schematic objects and simulations results corresponding to the design rule violations on a schematic representation of at least a portion of the design.

13. A method according to claim 12, further comprising:

providing an expert system;

providing the indications of and information about the design rule violations to the expert system;

forming, by means of the expert system, suggestions for alterations to the design which correct or eliminate the design rule violation; and

displaying the suggested design alterations.

14. An ECAD system for creating and validating a structural description of an electronic system from a higher level, behavior-oriented description thereof, comprising:

means for entering on an ECAD system a specification for a design of desired behavior of an electronic system, including timing goals, in a high-level, behavior-oriented language;

means for simulating and changing the design of the electronic system at the behavioral level until the desired behavior is obtained;

means for displaying the design of at least a portion of the electronic system as a plurality of graphical objects forming a schematic diagram and simultaneously displaying simulation data on the schematic diagram adjacent to graphical objects to which the simulation data applies;

means for partitioning the design of the device into a number of architectural blocks and constraining the architectural choices to those which meet the timing goals; and

means for directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a netlist or gate-level description of the design.

15. An ECAD system according to claim 14, wherein:

the electronic circuit diagram represents at least a portion of the electronic system; and

the simulation data represents signals corresponding to the portion of the electronic system represented by the electronic circuit diagram.

16. An ECAD system according to claim 14, wherein

the means for simultaneously displaying an electronic circuit diagram and simulation data further comprises:

a computer processor, including means for storing graphical objects;

graphical display means, connected to said computer processor, for displaying the graphical objects;

a portion of said graphical objects being pre-defined graphical objects accessible to said computer processor, each representing a particular schematic symbol, and each having a plurality of input and/or output nodes to which input and/or output signals may be associated;

means for graphically indicating interconnections (nets) between said input and output nodes of said graphical object on said graphical display means;

means for enabling a problem solving user to manipulate or arrange said pre-defined graphical objects on said graphical display means in the form of a schematic diagram, such that said schematic diagram may be viewed on said graphic display means either in whole or in part; and

means for enabling the problem solving user to create, delete or modify said graphical indications of interconnections between said graphical objects;

wherein;

the computer processor further includes;

a plurality of executable simulation models;

means for representing the state of interconnections between said graphical objects in the form of a net-list;

means for representing the state of interconnections between said graphical objects in the form of signal paths between simulation models;

means for specifying a signal state on any input or output node of said graphical objects;

means for specifying a signal state on any of said graphical interconnections (nets) between said input and output nodes of said graphical objects whereby said signal state is simultaneously applied to all input and output nodes connected thereto;

means for specifying an identified portion of said schematic diagram to be simulated;

means for specifying a simulation duration in the form a starting condition, or for specifying starting conditions and a stopping condition, or for specifying stopping conditions;

means for executing a simulation of the identified portion of said schematic diagram according to said starting and stopping conditions; and

means for displaying, on said schematic diagram on said graphical display means, the end states of said simulation such that the state data corresponding to the output nodes of each of said graphical objects is displayed adjacent thereto and for displaying on said graphical display means real-time timing information and net values, and for displaying on said graphical display means the input, output and results of the simulation.

17. An ECAD system according to claim 16, wherein:

the executable simulation models are provided to the computer processor as user-prepared simulation stimuli in the form of a data file or data list.

18. An ECAD system according to claim 17, further comprising:

means for displaying, on said graphical display means, simulation results in the form of a waveform diagram (timing diagram) such that the waveform pertaining to each of the output nodes of each of said graphical objects is displayed adjacent thereto.

19. An ECAD system according to claim 18, further comprising:

means for grouping said waveform displays into a single composite timing diagram in a single area on said schematic diagram, and for displaying said composite timing diagram on said graphical display means.

20. An ECAD system according to claim 16, further comprising:

means for enabling the problem solving user to specify a group of nodes or nets whose simulation results are to be collected in tabular form on said schematic diagram such that a state table is formed as the simulation(s) is(are) run.

21. An ECAD system according to claim 16, further comprising:

means for displaying, on said graphical display means, state performance loading drive strengths and other useful data on selected object nodes of each object.

22. An ECAD system according to claim 16, further comprising:

means for enabling the problem solving user to move through the interactive simulation in defined steps, or increments of the lowest system granularity.

23. An ECAD system according to claim 16, further comprising:

means for enabling the problem solving user to move through the interactive simulation in defined steps related to clock cycles.