Design rule checking system and method
First Claim
1. A method for performing design rule checking for an integrated circuit layout having been subjected to optical proximity correction OPC so that the integrated circuit layout includes OPC features, comprising:
- taking said integrated circuit layout including OPC features;
generating a simulation of an exposure made using said integrated circuit layout;
using said simulation to construct a second layout data; and
performing design rule checking of said second layout data.
3 Assignments
0 Petitions
Accused Products
Abstract
A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.
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Citations
11 Claims
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1. A method for performing design rule checking for an integrated circuit layout having been subjected to optical proximity correction OPC so that the integrated circuit layout includes OPC features, comprising:
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taking said integrated circuit layout including OPC features;
generating a simulation of an exposure made using said integrated circuit layout;
using said simulation to construct a second layout data; and
performing design rule checking of said second layout data. - View Dependent Claims (2, 3, 4, 5)
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6. A method for producing an integrated circuit layout, comprising:
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subjecting a layout to optical proximity correction OPC to produce an integrated circuit layout including OPC features;
generating a simulation of an exposure made using said integrated circuit layout;
using said simulation to construct a second layout data;
performing design rule checking of said second layout data; and
correcting said integrated circuit layout based upon results of said design rule checking. - View Dependent Claims (7, 8, 9, 10, 11)
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Specification