Semiconductor device

• US 6,472,685 B2
• Filed: 12/02/1998
• Issued: 10/29/2002
• Est. Priority Date: 12/03/1997
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takagi, Takeshi
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/203,098
• Publication Number:
  US 20020011628A1
• Time in Patent Office: 1,427 Days
• Field of Search: 157/77, 157/289, 157/369, 157/371
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

A first silicon layer (Si layer), a second silicon layer (Si₁C_y layer) containing carbon and a third silicon layer not containing carbon are stacked in this order on a silicon substrate. Since the lattice constant of the Si_1-yC_y layer is smaller than that of the Si layer, the conduction band and the valence band of the second silicon layer receive a tensile strain to be split. Electrons having a smaller effective mass, which have been induced by an electric field applied to a gate electrode, are confined in the second silicon layer, and move in the channel direction. Thus, an n-MOSFET having extremely high mobility can be obtained. Furthermore, if the second silicon layer is made of Si_l-x-yGe_xC_y, a structure suitable for a high-performance CMOS device can be formed. A high-performance field effect transistor can be provided at lower costs by using a heterojunction structure mainly composed of silicon.

Claims

1. A semiconductor device comprising an n-channel and a p-channel field effect transistor on a substrate, wherein the n-channel field effect transistor includes:

a first silicon layer formed on a substrate;

a first SiGeC layer in which an n-channel is formed, and which is formed on the first silicon layer, contains carbon and germanium and has received a tensile strain from the first silicon layer; and

a gate electrode formed over the first SiGeC layer, the p-channel field effect transistor including;

a second silicon layer formed on a substrate;

a second SiGeC layer in which a p-channel is formed, and which is formed on the second silicon layer, contains carbon and germanium and has received a tensile strain from the second silicon layer; and

a gate electrode formed over the second SiGeC layer,

wherein the semiconductor device functions as a complementary device.

2. The semiconductor device of claim 1, wherein electrons are confined by a heterobarrier formed between the first silicon layer and the first SiGeC layer of the n-channel field effect transistor;

and holes are confined in the second SiGeC layer of the p-channel field effect transistor.

3. The semiconductor device of claim 1, further comprising a heavily doped layer which is formed in the first silicon layer in the vicinity of the first SiGeC layer and contains a high-concentration n-type dopant;

and a heavily doped layer which is formed in the second silicon layer in the vicinity of the second SiGeC layer and contains a high-concentration p-type dopant.

4. The semiconductor device of claim 2, wherein the first SiGeC layer is a quantum well.

5. The semiconductor device of claim 1, further comprising a third silicon layer which is formed on the first SiGeC layer and under the gate electrode and applies a tensile strain to the first SiGeC layer;

and

a fourth silicon layer which is formed on the second SiGeC layer and under the gate electrode and applies a tensile strain to the second SiGeC layer,

wherein electrons are confined in the first SiGeC layer by a heterobarrier formed in a boundary between the first SiGeC layer and the third silicon layer, and

wherein holes are confined in the second SiGeC layer by a heterobarrier formed in a boundary between the second SiGeC layer and the fourth silicon layer.

6. The semiconductor device of claim 1, further comprising a heavily doped layer which is formed in the third silicon layer in the vicinity of the first SiGeC layer and contains a high-concentration n-type dopant;

and a heavily doped layer which is formed in the fourth silicon layer in the vicinity of the second SiGeC layer and contains a high-concentration p-type dopant.

7. The semiconductor device of claim 1, further comprising a gate insulating film formed under an n-gate electrode and a second gate insulating film formed under a p-gate electrode.

8. The semiconductor device of claim 1, wherein the thickness of the first SiGeC layer is smaller than a critical thickness which is determined by the composition of carbon and above which dislocations are generated.