Semiconductor device and method of manufacturing the same

• US 6,472,693 B1
• Filed: 10/27/2000
• Issued: 10/29/2002
• Est. Priority Date: 04/27/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki, Tomomatsu, Yoshifumi
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US09/696,963
• Time in Patent Office: 732 Days
• Field of Search: 257/130, 257/133, 257/138, 257/139, 257/142, 257/147, 257/155, 257/212, 257/296, 257/335, 257/107, 257/167
• US Class Current: 257/167
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly, an object of the present invention is to reduce an ON voltage while ensuring a wide operating area and sustaining a high breakdown voltage. To achieve this object, a semiconductor base body is divided into a first MOS region and a second MOS region. In the first MOS region, a p base layer, an n⁺ emitter layer and a p⁺ layer are provided in an upper main surface of the semiconductor base body. In the second MOS region, a p base layer, an n layer and a p⁺ layer are provided. When a positive gate voltage is applied to a gate electrode in order to turn on the device, since the p base layer and the emitter electrode are cut off, a main current does not flow in the p base layer. Therefore, a hole accumulation effect is enhanced and the ON voltage is reduced. When a negative gate voltage is applied in order to turn off the device, since a channel region is inverted, the main current constituted of residual carriers flows in both p base layers. Therefore, a wide operating area is ensured. Since no n layer surrounding the p base layer exists, unlike in a CSTBT, there is no problem of degradation in breakdown voltage.

Claims

1. A semiconductor device, comprising:

a semiconductor base body defining an upper main surface and a lower main surface,

wherein said semiconductor base body comprises

a first semiconductor layer of a first conductivity type exposed to said lower main surface;

a second semiconductor layer of a second conductivity type formed on said first semiconductor layer and exposed to said upper main surface;

a third semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer;

a fourth semiconductor layer of the second conductivity type selectively formed in a surface to which said third semiconductor layer is exposed, being shallower than said third semiconductor layer and inside said third semiconductor layer;

a fifth semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer and away from said third semiconductor layer;

a sixth semiconductor layer of the second conductivity type selectively formed in a surface to which said fifth semiconductor layer is exposed, being shallower than said fifth semiconductor layer and inside said fifth semiconductor layer; and

a seventh semiconductor layer of the first conductivity type selectively formed in a surface to which said sixth semiconductor layer is exposed, being shallower than said sixth semiconductor layer and inside said sixth semiconductor layer,

wherein a surface to which said third semiconductor layer is exposed in said upper surface includes a first region and a second region separated by said fourth semiconductor layer, and at least said second region of them is sandwiched by a surface to which said fourth semiconductor layer is exposed and a surface to which said second semiconductor layer is exposed,

said device further comprising;

a first gate electrode opposed to said second region with a first insulating film sandwiched therebetween;

a second gate electrode opposed to a surface to which said sixth semiconductor layer is exposed in said upper surface with a second insulating film sandwiched therebetween;

a first main electrode connected to said first region, said fourth semiconductor layer and said seventh semiconductor layer; and

a second main electrode connected to sa id lower main surface, and

wherein a transistor including said second semiconductor layer, said fifth semiconductor layer and said sixth semiconductor layer does not operate even when a predetermined voltage is applied to said second gate electrode and said first main electrode, respectively.

2. The semiconductor device according to claim 1, wherein

said first gate electrode and said second gate electrode are electrically connected to each other.

3. The semiconductor device according to claim 2, wherein

said first insulating film and said second insulating film are contiguously coupled to form a single insulating film, and said first gate electrode and said second gate electrode are contiguously coupled to form a single gate electrode, and

a surface to which said second semiconductor layer is exposed with the same sandwiched between said third semiconductor layer and said seventh semiconductor layer in said upper main surface is covered with said single gate electrode with said single insulating film sandwiched therebetween.

4. The semiconductor device according to claim 2, wherein

an area of said first gate electrode covering said upper main surface is larger that of said second gate electrode covering said upper main surface, and said first gate electrode and said second gate electrode are connected to each other at an end portion along said upper main surface.

5. The semiconductor device according to claim 1, wherein

said first gate electrode and said second gate electrode are electrically insulated from each other.

6. The semiconductor device according to claim 1, wherein

said semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type formed in said surface to which said sixth semiconductor layer is exposed in said upper main surface.

7. The semiconductor device according to claim 1, wherein

said semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type selectively formed in an exposed surface which is a surface to which said second semiconductor layer is exposed in said upper main surface, being shallower than said second semiconductor layer and away from both said third and fifth semiconductor layers.

8. The semiconductor device according to claim 7, wherein

said first insulating film and said first gate electrode are so extended as to also cover a portion adjacent to said third semiconductor layer in said exposed surface, and said second insulating film and said second gate electrode are so extended as to also cover a portion adjacent to said fifth semiconductor layer in said exposed surface, and

a surface portion covered with neither said first gate electrode nor said second gate electrode exists in said exposed surface, and said eighth semiconductor layer is selectively formed in a region including said surface portion in said exposed surface.

9. The semiconductor device according to claim 8, wherein

said third semiconductor layer, said fifth semiconductor layer and said eighth semiconductor layer are identical in depth and impurity concentration with one another.

10. The semiconductor device according to claim 1, wherein

a multilayer structure including said fifth, sixth and seventh semiconductor layers is divided into a plurality of unit multilayer structures formed away from one another,

said second insulating film and said second gate electrode comprise a plurality of unit second insulating films and a plurality of unit second gate electrodes, respectively,

any one of said plurality of unit second gate electrodes is opposed to a surface to which a portion of said sixth semiconductor layer included in corresponding one of said plurality of unit multilayer structures is exposed in said upper main surface with corresponding one of said plurality of unit second insulating films sandwiched therebetween, and

said first main electrode is connected to a portion of said seventh semiconductor layer included in each of said plurality of unit multilayer structures.

11. The semiconductor device according to claim 1, wherein

a multilayer structure including said fifth, sixth and seventh semiconductor layers is so annularly formed as to surround said third semiconductor layer.

12. The semiconductor device according to claim 1, wherein

said semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type having an impurity concentration higher than that of said third semiconductor layer, selectively formed in a region inside edges of said third semiconductor layer in said upper main surface, being exposed to said first region and not exposed to said second region, and

said first main electrode is connected to said third semiconductor layer through said eighth semiconductor layer.

13. The semiconductor device according to claim 12, wherein

said seventh semiconductor layer and said eighth semiconductor layer are identical in depth and impurity concentration with each other.

14. The semiconductor device according to claim 1, wherein

said third semiconductor layer and said fifth semiconductor layer are identical in depth and impurity concentration with each other.

15. A semiconductor device, comprising:

a semiconductor base body defining an upper main surface and a lower main surface,

wherein said semiconductor base body comprises

a first semiconductor layer of a first conductivity type exposed to said lower main surface;

a second semiconductor layer of a second conductivity type formed on said first semiconductor layer and exposed to said upper main surface;

a third semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer;

a fourth semiconductor layer of the second conductivity type selectively formed in a surface to which said third semiconductor layer is exposed, being shallower than said third semiconductor layer and inside said third semiconductor layer;

a fifth semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer and away from said third semiconductor layer;

a sixth semiconductor layer of the second conductivity type selectively formed in a surface to which said fifth semiconductor layer is exposed, being shallower than said fifth semiconductor layer and inside said fifth semiconductor layer; and

a seventh semiconductor layer of the first conductivity type selectively formed in a surface to which said sixth semiconductor layer is exposed, being shallower than said sixth semiconductor layer and inside said sixth semiconductor layer,

wherein a surface to which said third semiconductor layer is exposed in said upper surface includes a first region and a second region separated by said fourth semiconductor layer, and at least said second region of them is sandwiched by a surface to which said fourth semiconductor layer is exposed and a surface to which said second semiconductor layer is exposed,

said device further comprising;

a first gate electrode opposed to said second region with a first insulating film sandwiched therebetween;

a second gate electrode opposed to a surface to which said sixth semiconductor layer is exposed in said upper surface with a second insulating film sandwiched therebetween;

a first main electrode connected to said first region, said fourth semiconductor layer and said seventh semiconductor layer; and

a second main electrode connected to said lower main surface, and

wherein said sixth semiconductor layer and said first main electrode are not in contact with each other.

16. The semiconductor device according to claim 15, wherein said first gate electrode and said second gate electrode are electrically connected to each other.

17. The semiconductor device according to claim 16,

wherein said first insulating film and said second insulating film are contiguously coupled to form a single insulating film, and said first gate electrode and said second gate electrode are contiguously coupled to form a single gate electrode, and

a surface to which said second semiconductor layer is exposed with the same sandwiched between said third semiconductor layer and said seventh semiconductor layer in said upper main surface is covered with said single gate electrode with said single insulating film sandwiched therebetween.

18. The semiconductor device according to claim 16, wherein

an area of said first gate electrode covering said upper main surface is larger that of said second gate electrode covering said upper main surface, and said first gate electrode and said second gate electrode are connected to each other at an end portion along said upper main surface.

19. The semiconductor device according to claim 15, wherein

said first gate electrode and said second gate electrode are electrically insulated from each other.

20. The semiconductor device according to claim 15, wherein

said semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type formed in said surface to which said sixth semiconductor layer is exposed in said upper main surface.

21. The semiconductor device according to claim 15, wherein

said semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type selectively formed in an exposed surface which is a surface to which said second semiconductor layer is exposed in said upper main surface, being shallower than said second semiconductor layer and away from both said third and fifth semiconductor layers.

22. The semiconductor device according to claim 21, wherein

said first insulating film and said first gate electrode are so extended as to also cover a portion adjacent to said third semiconductor layer in said exposed surface, and said second insulating film and said second gate electrode are so extended as to also cover a portion adjacent to said fifth semiconductor layer in said exposed surface, and

a surface portion covered with neither said first gate electrode nor said second gate electrode exists in said exposed surface, and said eighth semiconductor layer is selectively formed in a region including said surface portion in said exposed surface.

23. The semiconductor device according to claim 22, wherein

said third semiconductor layer, said fifth semiconductor layer and said eighth semiconductor layer are identical in depth and impurity concentration with one another.

24. The semiconductor device according to claim 15, wherein

a multilayer structure including said fifth, sixth and seventh semiconductor layers is divided into a plurality of unit multilayer structures formed away from one another, said second insulating film and said second gate electrode comprise a plurality of unit second insulating films and a plurality of unit second gate electrodes, respectively,

any one of said plurality of unit second gate electrodes is opposed to a surface to which a portion of said sixth semiconductor layer included in corresponding one of said plurality of unit multilayer structures is exposed in said upper main surface with corresponding one of said plurality of unit second insulating films sandwiched therebetween, and

said first main electrode is connected to a portion of said seventh semiconductor layer included in each of said plurality of unit multilayer structures.

25. The semiconductor device according to claim 15, wherein

a multilayer structure including said fifth, sixth and seventh semiconductor layers is so annularly formed as to surround said third semiconductor layer.

26. The semiconductor device according to claim 15, wherein

said semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type having an impurity concentration higher than that of said third semiconductor layer, selectively formed in a region inside edges of said third semiconductor layer in said upper main surface, being exposed to said first region and not exposed to said second region, and

said first main electrode is connected to said third semiconductor layer through said eighth semiconductor layer.

27. The semiconductor device according to claim 26, wherein

said seventh semiconductor layer and said eighth semiconductor layer are identical in depth and impurity concentration with each other.

28. The semiconductor device according to claim 15, wherein

said third semiconductor layer and said fifth semiconductor layer are identical in depth and impurity concentration with each other.