Triple class E Doherty amplifier topology for high efficiency signal transmitters

• US 6,472,934 B1
• Filed: 12/29/2000
• Issued: 10/29/2002
• Est. Priority Date: 12/29/2000
• Status: Expired due to Term

• Current Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Pehlke, David R.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHANH V
• Application Number:
  US09/752,178
• Time in Patent Office: 669 Days
• Field of Search: 330/10, 330/124.R, 330/207.D, 330/295, 332/103, 332/145
• US Class Current: 330/10
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 2200/391 the output circuit of an amplifying stage comprising an LC-network
• CPC Class Codes: H03F 3/2176 Class E amplifiers

Abstract

A Doherty amplifier circuit is provided comprising at least three class E amplifiers receiving separated amplitude and phase information from at least one signal source. At least one first impedance adjustment device is linked between the signal source and the inputs to at least two of the amplifiers, and a plurality of second impedance adjustment devices is linked to the outputs of the amplifiers to combine the outputs into an output of the circuit. In this way, a scheme for efficient amplification of amplitude modulated waveforms is achieved across a wide dynamic range and for a large peak-to-average ratio using only input modulated techniques.

Claims

1. An amplifier circuit comprising:

at least three class E amplifiers receiving separated amplitude and phase information from at least one signal source;

at least one first impedance adjustment device linked between said at least one signal source and the inputs to at least two of said class E amplifiers; and

a plurality of second impedance adjustment devices linked to the outputs of said class E amplifiers to combine said outputs into an output of said circuit.

2. The amplifier circuit of claim 1 wherein said circuit is configured to allow one of said class E amplifiers to saturate prior to saturation of others of said class E amplifiers.

3. The amplifier circuit of claim 2 wherein said signal source further comprises a digital signal processor producing output signals.

4. The amplifier circuit of claim 3 wherein said class E amplifiers further comprise a first, a second and a third amplifier, said first amplifier functioning as a carrier amplifier receiving a first amplitude-modulated baseband signal from said digital signal processor, said second and said third amplifiers receiving a shared amplitude-modulated baseband signal from said digital signal processor.

5. The amplifier circuit of claim 4 wherein each of said class E amplifiers is configured to utilize an envelope signal to adjust its individual output power level.

6. The amplifier circuit of claim 5 wherein said impedance adjustment devices further comprise quarter-wave transformer lines.

7. The circuit of claim 6 further comprising:

a control device for at least one of said class E amplifiers for receiving amplitude information or phase information from a primary waveform, and

a plurality of switching devices in communication with said control device and said at least one class E amplifier, said switching devices each having a different current resistance;

wherein said control device uses said information to select an active switching device to create a secondary waveform for input to the matching network of said at least one amplifier.

8. The circuit of claim 7 wherein said switching devices are transistors each having a gate, and said control device controls said switching devices by providing said information at the gate of said switching device.

9. The circuit of claim 3 further comprising:

a feedback loop for sensing VSWR reflection from an antenna in communication with the outputs of said class E amplifiers, said feedback loop in communication with said digital signals processor;

wherein said digital signal processor adjusts its output signals to correct for said VSWR reflection.

10. The circuit of claim 1 wherein at least two of said class E amplifiers have different output power ratings.

11. An amplifier circuit comprising:

at least one signal source producing a plurality of digital amplitude modulation signals and a digital phase modulated signal;

a first class E carrier amplifier linked to receive one of said amplitude modulation signals and said phase modulation signal;

a first class E peaking amplifier linked to receive another of said amplitude modulation signals, said first peaking amplifier further receiving said phase modulation signal via one or more impedance adjusting devices;

a second class E peaking amplifier linked to receive another of said amplitude modulation signals, said second peaking amplifier further receiving said phase modulation signal via one or more impedance adjusting devices; and

a combining circuit linking the outputs of said amplifiers via one or more impedance adjusting devices.

12. The circuit of claim 11 further comprising envelope adjustment circuitry to adjust the power level for each amplifier in said circuit.

13. The circuit of claim 11 wherein said signal source further comprises at least one digital signal processor producing at least one output signal.

14. The circuit of claim 11 further comprising means for modulating the input to at least one of said amplifiers.

15. The circuit of claim 11 further comprising a third class E peaking amplifier linked to receive another of said amplitude modulation signals, said third peaking amplifier further receiving said phase modulation signal via one or more impedance adjusting devices.

16. The circuit of claim 13 further comprising:

a feedback loop for sensing VSWR reflection from an antenna in communication with said amplifiers, said feedback loop in communication with said digital signal processor;

wherein said digital signal processor adjusts said at least one output signal to correct for said VSWR reflection.

17. The circuit of claim 11 wherein said carrier amplifier and said first peaking amplifier have different output power ratings.

18. A method of providing high-efficiency signal amplification, said method comprising the steps of:

providing a first digital amplitude waveform to a class E carrier amplifier;

providing a first digital phase waveform to a first class E peaking amplifier;

providing a second digital phase waveform to a second class E peaking amplifier;

providing a shared digital phase waveform to said carrier and peaking amplifiers; and

combining the outputs of said carrier and peaking amplifiers via one or more impedance adjusting devices to produce an amplified signal output.

19. The method of claim 18 further comprising the step of adjusting the impedance of the shared digital phase waveform via one or more impedance adjustment devices before providing said waveform to said peaking amplifiers.

20. The method of claim 19 further comprising the step of providing a third digital phase waveform to a third class E peaking amplifier.

21. The method of claim 18 further comprising the steps of:

sensing VSWR reflection from an antenna in communication with said signal output; and

adjusting at least one of said waveforms before providing said waveforms to said carrier and peaking amplifiers to correct for said VSWR reflection.