PWM power amplifier
First Claim
1. A PWM power amplifier, comprising:
- at least one PCM/PWM converter which is fed by PCM digital input signals and produces PWM digital output signals, and at least one final stage of power amplification of the PWM digital signals in output from said at least one PCM/PWM converter, said at least one PCM/PWM converter comprising a counter fed with at least one clock signal produced by a clock generator device and comprising a digital comparator suitable for comparing said PCM digital input signals of said at least one PCM/PWM converter with a digital comparison signal produced by said counter and producing in output said PWM digital signals, said clock generator device comprising a pulse generator device and an oscillator, said pulse generator device receiving a signal at a frequency equal to the frequency of said PCM digital input signals of said at least one PCM/PWM converter and producing in output reset pulses, said reset pulses being sent in input to said oscillator producing in output said at least one clock signal.
1 Assignment
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Accused Products
Abstract
A PWM power amplifier having at least one PCM/PWM converter fed by PCM digital input signals and producing PWM digital output signals, and at least one power amplification final stage of the PWM digital output signals. At least one PCM/PWM converterincludes a counter fed with at least one clock signal produced by a clock generator device and having a digital comparator suitable for comparing the PCM digital input signals of at least one PCM/PWM converter with a digital comparison signal produced by the counter and producing in output the PWM digital signals. The clock generator device includes a pulse generator device and an oscillator; the pulse generator device receives a signal at a frequency that is equal to the frequency of the PCM digital input signals of the at least one PCM/PWM converter and produces in output reset pulses. The reset pulses are sent in input to the oscillator, which produces in output the at least one clock signal.
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Citations
19 Claims
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1. A PWM power amplifier, comprising:
- at least one PCM/PWM converter which is fed by PCM digital input signals and produces PWM digital output signals, and at least one final stage of power amplification of the PWM digital signals in output from said at least one PCM/PWM converter, said at least one PCM/PWM converter comprising a counter fed with at least one clock signal produced by a clock generator device and comprising a digital comparator suitable for comparing said PCM digital input signals of said at least one PCM/PWM converter with a digital comparison signal produced by said counter and producing in output said PWM digital signals, said clock generator device comprising a pulse generator device and an oscillator, said pulse generator device receiving a signal at a frequency equal to the frequency of said PCM digital input signals of said at least one PCM/PWM converter and producing in output reset pulses, said reset pulses being sent in input to said oscillator producing in output said at least one clock signal.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A PWM power amplifier, comprising:
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a digital signal circuit configured to receive in input a PCM signal with M bits and to convert the PCM signal with oversampling and noise shaping techniques into a PCM digital signal having N bits, where M>
N;
first and second PCM/PWM converters coupled to the digital signal circuit, the converters comprising a counter and a comparator, the counter configured to receive a clock signal and to generate a digital comparison signal, and the comparator configured to receive the digital comparison signal and at least a portion of the PCM digital signal and to generate first and second PWM digital signals as output of the first and second PCM/PWM converters, respectively;
a clock generator circuit comprising a pulse generator device and an oscillator, the pulse generator device receiving a signal at a frequency equal to a frequency of the PCM signal and to generate output reset pulses, and an oscillator configured to receive the output reset pulses and to generate the clock signal; and
a final stage configured to receive a combination of the first and second PWM digital signals and to provide power amplification thereof in an output. - View Dependent Claims (16, 17)
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18. A PWM power amplifier, comprising:
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a digital signal circuit configured to receive in input a PCM signal with M bits and to convert the PCM signal with oversampling and noise shaping techniques into a PCM digital signal having N bits, where M>
N;
first and second PCM/PWM converters coupled to the digital signal circuit, the converters comprising a counter and a comparator, the counter configured to receive a clock signal and to generate a digital comparison signal, and the comparator configured to receive the digital comparison signal and at least a portion of the PCM digital signal and to generate first and second PWM digital signals as output of the first and second PCM/PWM converters, respectively;
a clock generator circuit comprising a pulse generator device and an oscillator, the pulse generator device receiving a signal at a frequency equal to a frequency of the PCM signal and to generate output reset pulses, and an oscillator configured to receive the output reset pulses and to generate the clock signal, the clock signal having a clock frequency equal to the product of the first frequency by the power in base two of the number of bits of the PCM signal portion input into one of the first and second PCM/PWM converters, the counter receiving the clock signal and configured to generate the digital comparison output signal in the form of at least one ramp of digital values at an identical or halved frequency compared to the first frequency; and
a final stage configured to receive a combination of the first and second PWM digital signals and to provide power amplification thereof in an output.
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19. A PWM power amplifier, comprising:
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a digital signal circuit configured to receive in input a PCM signal with M bits and to convert the PCM signal with oversampling and noise shaping techniques into a PCM digital signal having N bits, where M>
N;
first and second PCM/PWM converters coupled to the digital signal circuit, the converters comprising a counter and a comparator, the counter configured to receive a clock signal and to generate a digital comparison signal, and the comparator configured to receive the digital comparison signal and at least a portion of the PCM digital signal and to generate first and second PWM digital signals as output of the first and second PCM/PWM converters, respectively;
a clock generator circuit comprising a pulse generator device and an oscillator, the pulse generator device receiving a signal at a first frequency equal to a frequency of the PCM signal and to generate output reset pulses, and an oscillator configured to receive the output reset pulses and to generate the clock signal, the clock signal having a frequency equal to the product of the first frequency by the power in base two of the number of bits of the PCM signal received by one of the first and second PCM/PWM converters, each of the first and second PCM/PWM converters comprising a double ramp type converter receiving the clock signal, and each counter being of the up/down type and having in input a ramp conversion signal and configured to generate in output the digital comparison signal comprising the number of bits of the portion of the PCM signal received by the respective counter, and further in the form of a succession of up and down ramps at a halved frequency of the first frequency; and
a first final stage configured to receive a combination of the first and second PWM digital signals and to provide power amplification thereof in an output, and a second final stage that is a duplicate of the first final stage and functioning in counter phase thereof and having an inversion signal input that receives an inversion of a combination of the PWM digital signals that is generated by a second and third pair of PCM/PWM double ramp converters that are duplicates of the first and second PCM/PWM converters and having the ramp inversion signal inverted and to generate a power amplification thereof.
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Specification