Semiconductor integrated circuit and nonvolatile semiconductor memory

• US 6,473,321 B2
• Filed: 06/19/2001
• Issued: 10/29/2002
• Est. Priority Date: 07/03/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Sato, Hiroshi, Ishii, Tatsuya, Noda, Satoshi, Ogino, Takashi, Kishimoto, Jiro, Kubono, Shoji
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US09/883,237
• Publication Number:
  US 20020001207A1
• Time in Patent Office: 497 Days
• Field of Search: 363/59, 363/60, 327/536, 327/589, 327/389, 327/390, 365/226, 365/227, 365/189.09, 365/189.11
• US Class Current: 363/59
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Abstract

For a semiconductor integrated circuit having an internal booster circuit such as a flash memory, voltage booster circuits capable of generating a boosted voltage 10 times or more as high as a relatively low source voltage is to be realized. Charge pumps for carrying out first stage voltage boosting on the basis of a source voltage are configured of parallel capacity type units, and charge pumps for carrying out second stage voltage boosting on the basis of the boosted voltage generated by the first charge pumps are configured of serial capacity type units.

Claims

1. A semiconductor integrated circuit comprising a voltage booster circuit for generating a boosted voltage on the basis of a source voltage supplied from outside, wherein:

said voltage booster circuit comprises;

a first voltage booster circuit, including parallel capacity type charge pumps, for carrying out a first stage of voltage boosting on the basis of the source voltage; and

a second voltage booster circuit, including serial capacity type charge pumps, for carrying out a second stage of voltage boosting on the basis of the boosted voltage generated by said first voltage booster circuit.

2. A semiconductor integrated circuit according to claim 1, wherein said first voltage booster circuit comprises:

a first parallel capacity type charge pump in which a circuit on a side to which the generated voltage is supplied is capacitive loads; and

a second parallel capacity type charge pump in which a circuit on a side to which the generated voltage is supplied is resistive loads, and said second voltage booster circuit carries out second stage voltage boosting on the basis of the boosted voltage generated by said first parallel capacity type charge pump.

3. A semiconductor integrated circuit according to claim 2, wherein said second voltage booster circuit is provided with a first serial capacity type charge pump for generating a positive boosted voltage and a second serial capacity type charge pump for generating a negative boosted voltage.

4. A semiconductor integrated circuit according to claim 3, wherein the number of voltage boosting stages of said first and second parallel capacity type charge pumps is greater than the number of voltage boosting stages of said first and second serial capacity type charge pumps.

5. A semiconductor integrated circuit according to claim 4, wherein, in said first parallel capacity type charge pumps, their voltage boosting operation can be stopped in accordance with a first control signal.

6. A semiconductor integrated circuit according to claim 5, wherein, in said first serial capacity type charge pumps or second serial capacity type charge pumps, their voltage boosting operation can be stopped in accordance with a second control signal.

7. A semiconductor integrated circuit according to claim 6, wherein at least said second parallel capacity type charge pumps are comprised of a plurality of parallel capacity type charge pumps connected to one another in parallel, and are so configured that the number of operating charge pumps is determined according to the level of the source voltage.

8. A semiconductor integrated circuit according to claim 7, wherein said first parallel capacity type charge pumps and second parallel capacity type charge pumps are operated by a plurality of operating clock signals, and

said first voltage booster circuit is provided with an auxiliary voltage booster circuit for generating a boosted voltage lower than the boosted voltage generated by that first voltage booster circuit on the basis of the source voltage, and at least some of said plurality of operating clock signals are expanded in amplitude on the basis of the boosted voltage generated by said auxiliary voltage booster circuit.

9. A semiconductor integrated circuit according to claim 8, wherein said first serial capacity type charge pumps and second serial capacity type charge pumps are operated by a plurality of second operating clock signals, and

said second voltage booster circuit is provided with a second auxiliary voltage booster circuit for generating, on the basis of the boosted voltage generated by said first voltage booster circuit, a boosted voltage lower than the boosted voltage generated by that second voltage booster circuit, and at least some of said plurality of second operating clock signals are expanded in amplitude on the basis of the boosted voltage generated by said second auxiliary voltage booster circuit.

10. A semiconductor integrated circuit provided with a voltage booster circuit for generating a boosted voltage on the basis of a source voltage supplied from outside, wherein:

said voltage booster circuit comprises;

a first voltage booster circuit, including parallel capacity type charge pumps, for carrying out a first stage of voltage boosting on the basis of the source voltage; and

a second voltage booster circuit, including serial capacity type charge pumps, for carrying out a second stage of voltage boosting on the basis of the boosted voltage generated by said first voltage booster circuit;

booster capacities in said parallel capacity type charge pumps are;

capacities having, on the surface of a well region of the same first conductivity type as the well region of a second conductivity type over which MOSFETs of a first conductivity type are formed, MOSFETs of the second conductivity type and a contact region comprised of a semiconductor region of the same conductivity type as source and drain regions, and a conductive layer formed over the well region of said same conductivity type via an insulating film, wherein the well region of said same conductivity type is made a first electrode, said conductive layer is made a second electrode and said insulating film is made a dielectric, and

the insulating film of the first stage side booster capacity, out of the booster capacities of different stages of said parallel capacity type charge pumps, is thinner than the insulating film of the final stage side booster capacity.

11. A semiconductor integrated circuit according to claim 10, including a nonvolatile memory element having a floating gate electrode and a control gate electrode, wherein a threshold voltage varies according to injection or withdrawal of an electric charge into or from said floating gate electrode, and storing information according to that threshold voltage, and

said insulating film of said first stage side booster capacity has the same thickness as the insulating film underneath the floating gate electrode of said nonvolatile memory element.

12. A nonvolatile memory having a floating gate electrode and a control gate electrode, wherein a threshold voltage varies according to injection or withdrawal of an electric charge into or from said floating gate electrode, and provided with a nonvolatile memory element for storing information according to that threshold voltage and with voltage booster circuits for generating a boosted voltage on the basis of a source voltage supplied from outside, wherein:

said voltage booster circuits comprise a first voltage booster circuit, including parallel capacity type charge pumps, for carrying out first stage voltage boosting on the basis of the source voltage, and a second voltage booster circuit, including serial capacity type charge pumps, for carrying out second stage voltage boosting on the basis of the boosted voltage generated by said first voltage booster circuit;

,

said second voltage booster circuit generates;

a first boosted voltage for injecting electric charges into the floating gate electrode of said nonvolatile memory element by utilizing the FN tunnel phenomenon, and

a second boosted voltage for withdrawing electric charges from said floating gate electrode by utilizing the EN tunnel phenomenon.

13. A nonvolatile memory according to claim 12, wherein said first voltage booster circuit comprises:

a first parallel capacity type charge pump in which a circuit on a side to which the generated voltage is supplied is capacitive loads; and

a second parallel capacity type charge pump in which a circuit on a side to which the generated voltage is supplied is resistive loads, and said second voltage booster circuit carries out second stage voltage boosting on the basis of the boosted voltage generated by said first parallel capacity type charge pump.

14. A nonvolatile memory according to claim 13, wherein said second voltage booster circuit comprises:

a first serial capacity type charge pump for generating a positive boosted voltage for use in injecting electric charges into the floating gate electrode; and

a second serial capacity type charge pump for generating a negative boosted voltage for use in withdrawing electric charges from the floating gate electrode.

15. A nonvolatile memory according to claim 14, wherein said first parallel capacity type charge pump is configured so as to stop its voltage boosting operation, in writing or erasing data into or out of said nonvolatile memory element, on the basis of a first control signal.

16. A nonvolatile memory according to claim 15, wherein, in said first serial capacity type charge pump, its voltage boosting operation is stopped when data are erased from said nonvolatile memory element on the basis of a second control signal, and in said second serial capacity type charge pump, its voltage boosting operation is stopped when data are written into said nonvolatile memory element on the basis of said second control signal.

17. A nonvolatile memory device comprising:

a logic circuit including a decoder circuit;

a memory array having a plurality of word lines; and

a booster circuit including a first boost unit and a second boost unit,

wherein said first boost unit has a parallel capacity type charge pump and supplies a first voltage boosted from a source voltage to said logic circuit, and

wherein said second boost unit has a serial capacity type charge pump and supplies a second voltage boosted from said first voltage to said word line corresponding to an output of said decoder circuit.

18. a nonvolatile memory device according to claim 17,

wherein said second boost unit supplies said second voltage for programming data to a nonvolatile memory cell or for erasing data stored in said nonvolatile memory cell.

19. A nonvolatile memory device according to claim 18,

wherein said second boost unit stops boosting during reading of data from said nonvolatile memory cell.

20. A nonvolatile memory device according to claim 19,

wherein said second boost unit has a first charge pump and a second charge pump,

wherein said first charge pump is a serial capacity type charge pump and generates a positive voltage for said programming data, and

wherein said second charge pump is a serial capacity type charge pump and generates a negative voltage for said erasing data.

21. A nonvolatile memory device according to claim 20,

wherein said first charge pump stops boosting during erasing of data stored in said nonvolatile memory cell, and

wherein said second charge pump stops boosting during programming of data to said nonvolatile memory cell.

22. A nonvolatile memory device according to claim 21,

wherein said first boost unit has a third charge pump and a fourth charge pump,

wherein said third charge pump is said parallel capacity type charge pump and supplies said first voltage to said logic circuit, and

wherein said fourth charge pump is said parallel capacity type charge pump and supplies boosted voltage to said second boost unit.

23. A nonvolatile memory device according to claim 22,

wherein said fourth charge pump stops boosting during reading of data from said nonvolatile memory cell.