Semiconductor memory and method for accessing semiconductor memory
First Claim
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1. A semiconductor memory provided with ferroelectric layers, comprising:
- memory cells each comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;
buffer cells capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells; and
buffer circuits for transferring the data in the memory cells to the buffer cells and further writing the transferred data again to the memory cells.
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Abstract
A semiconductor memory provided with ferroelectric layers, that includes memory cells, buffer cells, and buffer circuits. The memory cells each include a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer cells are capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells. The buffer circuits are for transferring the data in the memory cells to the buffer cells and for further writing the transferred data again to the memory cells.
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Citations
20 Claims
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1. A semiconductor memory provided with ferroelectric layers, comprising:
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memory cells each comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;
buffer cells capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells; and
buffer circuits for transferring the data in the memory cells to the buffer cells and further writing the transferred data again to the memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor memory provided with ferroelectric layers, comprising:
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a plural number of memory cells arranged in a matrix each memory cell comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;
buffer cells capable of storing data from at least one line of the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells, wherein the buffer cells comprise ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer; and
buffer circuits for transferring the data in at least one line of the memory cells as a whole to the buffer cells and further writing the transferred data again to the memory cells, wherein each buffer circuit comprises;
a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.
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20. A semiconductor memory provided with ferroelectric layers, comprising:
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memory cells each comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;
buffer cells capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells, wherein the buffer cells comprise ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer; and
buffer circuits for transferring the data in the memory cells to the buffer cells and further writing the transferred data again to the memory cells, wherein each buffer circuit comprises;
a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.
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Specification