Semiconductor memory and method for accessing semiconductor memory

• US 6,473,329 B1
• Filed: 05/04/2000
• Issued: 10/29/2002
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakamura, Takashi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/530,727
• Time in Patent Office: 908 Days
• Field of Search: 365/145, 365/149, 365/222
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film

Abstract

A semiconductor memory provided with ferroelectric layers, that includes memory cells, buffer cells, and buffer circuits. The memory cells each include a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer cells are capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells. The buffer circuits are for transferring the data in the memory cells to the buffer cells and for further writing the transferred data again to the memory cells.

Claims

1. A semiconductor memory provided with ferroelectric layers, comprising:

memory cells each comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;

buffer cells capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells; and

buffer circuits for transferring the data in the memory cells to the buffer cells and further writing the transferred data again to the memory cells.

2. The semiconductor memory of claim 1, wherein a plural number of the memory cells are arranged as a matrix, the buffer cells are capable of storing data from at least one line of the memory cells, and each buffer circuit is capable of transferring data in at least one line of the memory cells as a whole to the buffer cells and writing again to the memory cells.

3. The semiconductor memory of claim 1, wherein the buffer cells comprise ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer.

4. The semiconductor memory of claim 3, wherein each buffer circuit comprises;

a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.

5. The semiconductor memory of claim 2, wherein the buffer cells comprise ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer.

6. The semiconductor memory of claim 5 wherein each buffer circuit comprises;

a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.

7. The semiconductor memory of claim 1, wherein buffer cells are positioned in one row parallel to a row of memory cells.

8. The semiconductor memory of claim 1, wherein each memory cell further comprises an insulation film between the ferroelectric layer and the semiconductor layer.

9. The semiconductor memory of claim 8, wherein the insulation layer is selected from the group consisting of SiO₂ and Si₃N₄.

10. The semiconductor memory of claim 8, wherein each memory cell further comprises a metallic layer between the ferroelectric layer and the isolation film.

11. The semiconductor memory of claim 4, wherein the first selection element is an FET.

12. The semiconductor memory of claim 11, wherein gates of the first selection elements are arranged in a row and connect to a first lead out.

13. The semiconductor memory of claim 4, wherein the second selection element is an FET.

14. The semiconductor memory of claim 13, wherein drains of the second selection elements connect to gates of the buffer cells.

15. The semiconductor memory of claim 13, wherein sources of the second selected elements are arranged in a row and connect to a second lead out.

16. The semiconductor memory of claim 13, wherein gates of the second selection elements connect to a third lead out.

17. The semiconductor memory of claim 3, wherein sources of the buffer cells connect to a fourth lead out.

18. The semiconductor memory of claim 1, wherein substrates of the memory cells connect to a fifth lead out.

19. A semiconductor memory provided with ferroelectric layers, comprising:

a plural number of memory cells arranged in a matrix each memory cell comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;

buffer cells capable of storing data from at least one line of the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells, wherein the buffer cells comprise ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer; and

buffer circuits for transferring the data in at least one line of the memory cells as a whole to the buffer cells and further writing the transferred data again to the memory cells,

wherein each buffer circuit comprises;

a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.

20. A semiconductor memory provided with ferroelectric layers, comprising:

memory cells each comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer;

buffer cells capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells, wherein the buffer cells comprise ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer; and

buffer circuits for transferring the data in the memory cells to the buffer cells and further writing the transferred data again to the memory cells,

wherein each buffer circuit comprises;

a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.