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Method and apparatus for fail-safe resynchronization with minimum latency

  • US 6,473,439 B1
  • Filed: 10/09/1998
  • Issued: 10/29/2002
  • Est. Priority Date: 10/10/1997
  • Status: Expired due to Fees
First Claim
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1. A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:

  • a receive clock domain circuit for providing the data clocked by the receive clock;

    a first latching circuit, coupled to an output of the receive clock domain circuit, for latching the data on a first edge of the transmit clock;

    wherein the receive clock and transmit clock are mesochronous;

    a second latching circuit, coupled to the receive clock domain circuit in parallel with the first latching circuit, for latching the data on a second edge of the-transmit clock;

    a multiplexing circuit, having inputs coupled to outputs of the first and second latching circuits; and

    a phase measurement circuit, configured to measure a phase difference between the receive and transmit clocks and to provide a select signal to the multiplexer in accordance with the phase difference.

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