Local communication system and apparatus for use therein

• US 6,473,469 B1
• Filed: 04/19/1999
• Issued: 10/29/2002
• Est. Priority Date: 08/21/1997
• Status: Expired due to Fees

• Current Assignee: Communication & Control Electronics Limited
• Original Assignee: Communication & Control Electronics Limited
• Inventors: Leitch, James R.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US09/294,088
• Time in Patent Office: 1,289 Days
• Field of Search: 375/219, 375/220, 375/241, 375/242, 375/257, 375/279, 375/282, 375/308, 375/328, 375/333, 375/361
• US Class Current: 375/308
• CPC Class Codes: H04L 27/2057 with a separate carrier for each phase state
• CPC Class Codes: H04L 27/2335 using temporal properties of the received signal

Abstract

A local area network is based on a ring of twisted pair cable links (UTP), each carrying at least 1.4 Mbps gross data rate. Each station on the network includes an encoder and a following station includes a decoder for PSK (phase shift keying) modulated serial data. The encoder uses an analog sine wave oscillator and inverter for generating antiphase analog sine wave signals at a carrier frequency and a switching circuit for selecting between the carrier signals according to the data signal to be transmitted. The decoder may use a simple integrator and comparator arrangement. The encoder and decoder may be provided in the form of an adapter circuit, such that a network based on optical fibre can be replaced by a network based on twisted pair cable using the same digital circuits. Generation of the PSK waveform by analog circuitry rather than digital synthesis reduces radio frequency emissions to a level suitable for use in an automotive audio/video communications network.

Claims

1. A local communication system for transmitting a digital serial data signal of at least 1.4 Mbps gross data rate, the system comprising a first station including an encoder and a second station including a decoder connected to the encoder of the first station by electrical conductors, the encoder of the first station comprising:

carrier signal generating means for generating a carrier signal at a carrier frequency without using digital synthesis;

a phase shift keying (PSK) modulation circuit responsive to said digital serial data signal for selectively outputting one of (a) said carrier signal and (b) its inverse, dependent on the value of said digital serial data signal so as to generate a PSK waveform; and

driver means for imposing said PSK waveform on said conductors,

the decoder of the second station being a decoder for decoding said PSK waveform so as to recover the digital serial data signal.

2. A system as in claim 1 wherein said carrier frequency is related to the data rate of said serial data signal such that substantially an integral number of cycles of the carrier signal occur between transitions of the serial data signal.

3. A system as in claim 2 wherein said integral number takes the value one or two, depending on the data content of the serial data signal, and disregarding any special synchronisation patterns present in the serial data signal.

4. A system as in claim 1 wherein said carrier signal generating means is arranged to generate two sine wave signals in antiphase with one another and said PSK modulation circuit comprises a switching circuit responsive to said digital serial data signal for selectively outputting one of said sine wave signals, dependent on the value of said digital serial data signal.

5. A system as in claim 1 wherein said serial data signal is channel encoded so as to comprise either one or two transitions per data bit.

6. A system as in claim 1 wherein said serial data signal is channel encoded in differential form such that the recovered serial data signal is independent of inversion of the PSK waveform.

7. A system as in claim 1 wherein said carrier frequency is twice the gross data bit rate of said serial data signal.

8. A system as in claim 1 wherein said carrier frequency exceeds 5 MHz.

9. A system as in claim 1 wherein said carrier frequency exceeds 10 MHz.

10. A system as in claim 1 wherein said electrical conductors comprise a twisted pair cable, said driver means comprises a differential line driver, and said decoder includes a differential input circuit for rejection of common mode noise.

11. A system as in claim 1 wherein the encoder further comprises means for fixedly synchronising said carrier signal with said digital serial data signal.

12. A system as in claim 11 wherein transitions of said digital serial data signal are synchronised with zero crossing of said carrier signal.

13. A system as in claim 11 wherein said synchronising means comprises means for deriving a digital data clock signal from a sine wave signal within said carrier signal generating means, and for supplying said clock signal to a digital circuit so as to control release of said serial data signal.

14. A system as in claim 1 wherein said second receiving station further comprises means for recovering from said PSK waveform or from the decoded serial data signal a data clock signal for use in processing the recovered serial data signal.

15. A system as in claim 1 wherein one of said first and second stations includes an FM radio receiver.

16. A system as in claim 1 wherein one of said first and second stations includes a mobile telephone component.

17. A system as in claim 1 wherein said serial data signal includes digital audio data and said serial data signal is generated synchronously with the sampling periods of said audio data.

18. A system as in claim 1 wherein said second station further comprises:

digital circuit means for processing said recovered serial data signal and generating a second digital serial data signal; and

a second encoder for transmitting said second serial data signal over further conductors, said second encoder including second carrier signal generating means, a second PSK modulation circuit and second driver means equivalent to the encoder of the first station.

19. A system as in claim 18 wherein said digital circuit means comprises:

a digital network transceiver circuit integrated separately from said second encoder;

the digital circuit means comprising means for extracting a signal from the recovered serial data signal,

whereby the second serial data signal is synchronised with said serial data signal.

20. A system as in claim 19 wherein said second carrier signal generating means is arranged to generate a generated carrier signal fixedly synchronised with said second serial data signal.

21. A system as in claim 20 wherein said second carrier signal generating means comprises a phase comparator for comparing the phase of the generated carrier signal with that of said second digital serial data signal and for controlling the frequency of the generated carrier signal in response to an output of the phase comparator.

22. A system as in claim 21 wherein said second carrier signal generating means generates plural sine wave signals.

23. A system as in claim 20, comprising a ring network of at least said first and second stations, each of the first and second stations comprising an encoder and decoder connected by conductors for communication with the decoder and encoder of next and previous stations of said ring network respectively.

24. A system as in claim 23 wherein:

each station includes synchronising means comprising means for deriving a digital data clock from a sine wave signal within said carrier signal generating means, and for supplying said digital data clock to digital circuit means so as to control release of said serial data signal,

each said carrier signal generating means comprises a phase comparator for comparing the phase of each thereat generated sine wave signal with that of the thereat recovered serial data signal and for controlling the frequency of the thereat generated sine wave signal in response to an output of the phase comparator; and

said synchronising means are used selectively, depending on whether the station is acting as a network master or network slave, respective.

25. An apparatus for reception of digital serial data having all the second station technical features of a system as in claim 18.

26. A system as in claim 1 wherein said decoder is a non-coherent decoder, comprising an intergrator circuit for intergrating said PSK waveform to recover said serial data signal.

27. An encoder for transmission of a digital serial data signal at a gross data rate of at least 1.4 Mbps, the encoder comprising:

carrier signal generating means for generating a carrier signal at a carrier frequency without using digital synthesis;

a phase shift keying (PSK) modulation circuit responsive to said digital serial data signal for selectively outputting one of (a) said carrier signal and (b) its inverse, dependent on the value of said digital serial data signal so as to generate a PSK waveform; and

driver means for imposing said PSK waveform on electrical conductors.

28. An adapter device for connecting a first digital data processing circuit to a second digital data processing circuit via a wired communications link, the adapter comprising a self-contained unit including:

analogue signal generating means for generating plural sine wave signals at a carrier frequency, the signals having predetermined different phases relative to one another;

clock generating means connected with said analogue signal generating means for generating at least one digital clock signal synchronised with at least one of said sine wave signals for application to said first digital data processing circuit;

switching means connected for receiving from said first digital data processing circuit a first digital serial data signal and for generating a first phase shift keying (PSK) modulated signal in accordance with the received first digital serial data signal by switching between different ones of said plural sine wave signals in response to transitions of said first digital serial data signal.

29. An adapter device as in claim 28 further comprising a differential line driver for applying said modulated signal to a pair of conductors forming said wired communication link.

30. An adapter device as in claim 28 further comprising means for receiving a second PSK modulated signal from an equivalent adapter device coupled to the second digital data processing circuit, and means for recovering therefrom a second digital serial data signal for supplying to said first digital data processing circuit.

31. An adapter device as in claim 30 wherein said analogue signal generating means includes means for synchronising said plural sine wave signals and said digital clock signal with received second modulated signal.

32. An adapter device as in claim 28 wherein said analogue signal generating means includes an analogue oscillator circuit for generating a sine wave signal at carrier frequency.

33. An adapter for connecting a first digital data processing circuit to a second digital data processing circuit via a wired communications link, the adapter comprising a self-contained unit including:

carrier signal generating means for generating a carrier signal at a carrier frequency;

clock generating means connected with said carrier signal generating means for generating at least one digital clock signal synchronised with said carrier signal for application to said digital data processing circuit;

phase shift keying (PSK) modulation means for receiving from said first digital data processing circuit a first digital serial data signal and for generating a first PSK modulated signal in accordance with the received first digital serial data signal by selectively outputting one of (a) said carrier signal and (b) its inverse, dependent on the value of said first digital serial data signal.

34. An adapter device as in claim 33 further comprising a differential line driver for applying said modulated signal to a pair of conductors forming said wired communications link.

35. An adapter device as in claim 33 further comprising means for receiving a second PSK modulated signal from an equivalent adapter device coupled to the second digital data processing circuit, and means for recovering therefrom a second digital serial data signal for supplying to said first digital data processing circuit.