×

Communication device with a self-calibrating sleep timer

  • US 6,473,607 B1
  • Filed: 04/30/1999
  • Issued: 10/29/2002
  • Est. Priority Date: 06/01/1998
  • Status: Active Grant
First Claim
Patent Images

1. A system for operating a battery operated communication device with reduced power consumption wherein the communication device is adapted to receive radio signals containing intermittently scheduled digital messages, the communication device comprisingreceiver means for frequency down conversion of the radio signals and demodulation of the digital messages;

  • a dual mode timer for continually maintaining system time while operating in one of two modes, the modes comprising an active mode and a sleep mode;

    controller data processing means for data processing of the demodulated message data to extract the messages;

    a reference oscillator for generating a reference clock, wherein the frequency of said reference clock is high enough to serve as clocking requirements for digital processing in the receiver and controller during the active mode, and wherein the frequency of the reference clock is responsive to input of an automatic frequency control word to the reference oscillator;

    a sleep oscillator for generating a frequency which is low relative to the frequency of the reference clock and wherein power consumption of the sleep oscillator is very low relative to the power consumption of the reference oscillator; and

    controller means for supervising operation of the communication device, wherein the supervision is executed by a microprocessor operation with program memory contained in a storage register, wherein the timer for continually maintaining system time while operating in one of two modes, comprises a reference counter for modulus counter means that counts cycles of the reference clock up to a modulus value stored in a reference counter modulus register and resetting to zero at the next clock count, the reference counter generating system time during active mode in units of reference clock number represented by the current value in the reference counter, the reference counter generating a frame epoch output at the time of the reset, the reference counter also generating shifts in system time in units of reference clock cycles when a modulus value other than nominal is written to the reference counter modulus register.

View all claims
  • 8 Assignments
Timeline View
Assignment View
    ×
    ×