Compact fault detecting system capable of detecting fault without omission

• US 6,473,722 B1
• Filed: 12/18/1998
• Issued: 10/29/2002
• Est. Priority Date: 12/18/1997
• Status: Expired due to Fees

• Current Assignee: HTC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakano, Hirotaka
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Charioui, Mohamed
• Application Number:
  US09/215,701
• Time in Patent Office: 1,411 Days
• Field of Search: 702/57, 702/58, 702/59, 702/185, 324/500, 324/512, 324/513, 714/25, 714/803, 714/804, 714/805, 714/128, 377/28
• US Class Current: 702/185
• CPC Class Codes: G01R 31/317 Testing of digital circuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A fault detection system applies known data to the input of a circuit being inspected for faults and examines the circuit output for expected results. Faults in a circuit are detected by receiving unexpected results at the circuit output. A fault detection circuit provides a fault signal that is enabled only when a reset line is activated. Activation of the reset line also prompts the known data to be applied to the circuit input. The known data can be derived from memory storage units that provide a known output upon activation of the reset signal. Accordingly, the system does not require parity bits or excessive hardware to provide fault detection for almost all modes of failure in a given circuit.

Claims

1. A fault detection system for detecting faults in a circuit, said fault detection system comprising:

a data storage element having a storage output;

a reset signal coupled to said storage element;

said storage element effective to apply a fault detection data value to said storage output when said reset signal is active;

said storage output coupled to a circuit input of said circuit;

a circuit output of said circuit providing an output signal related to said circuit input; and

a fault detector coupled to said circuit output, said fault detector operable to determine whether said circuit output includes a fault based on said circuit input when said fault detection data value is applied to said storage output.

2. A fault detection system according to claim 1, wherein said reset signal is coupled to said fault detector.

3. A fault detection system according to claim 2, wherein said reset signal enables said fault detector when said reset signal is active.

4. A fault detection system according to claim 2, further comprising:

a buffer element in said fault detector, said buffer element having a buffer output;

said buffer element holds a value of said reset signal when said reset signal is active; and

said buffer output enables a fault detector output.

5. A fault detection system according to claim 1, wherein said circuit output is univocally determined by said input.

6. A fault detection system according to claim 1, wherein said data storage element comprises a plurality of data storage elements, each of said data storage elements having a storage output coupled to a respective circuit input of said circuit.

7. A fault detection system according to claim 1, wherein said circuit comprises a plurality of circuits, each of said circuits having a circuit input and a circuit output, said storage output coupled to said circuit inputs, and said circuit outputs coupled to said fault detector.

8. A method of detecting a fault in a circuit, said method comprising:

activating a reset signal;

applying a fault detection data value to said circuit when a reset signal is active;

analyzing a circuit output of said circuit to detect a fault based on an expected value of said circuit output resulting from application of said fault detection data value; and

enunciating detected faults.

9. A method of detecting a fault according to claim 8, further comprising enabling fault detection by activation of said reset signal.