High performance communication controller for processing high speed data streams wherein execution of a task can be skipped if it involves fetching information from external memory bank

• US 6,473,808 B1
• Filed: 04/02/1999
• Issued: 10/29/2002
• Est. Priority Date: 04/02/1999
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hagai, Avi, Kurnick, Moti, Shalev, Avi, Weitz, Eliezer, Yeivin, Yoram
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/285,519
• Time in Patent Office: 1,306 Days
• Field of Search: 710/6, 710/22, 710/27, 710/240, 710/244, 710/264, 709/100, 709/102, 709/103, 709/107, 709/223, 711/5, 711/100
• US Class Current: 710/6
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.

Claims

1. A high speed communication controller, for receiving, transmitting and processing high speed data streams, the data streams being comprised of frames, the communication controller being adapted to be coupled to a plurality of communication channels and to a first and a second external buses, the communication controller comprising:

a first processor for controlling data stream transactions, wherein the first processor controls a transaction of a frame by executing a task;

a second processor for handling high level management and communication protocol functions; and

a scheduler, coupled to first processor, for sensing if there is a need to execute a task, and for selecting a selected task to be executed by the first processor,

wherein the first processor stops to execute a task when the execution of the task involves fetching information from the external memory bank.

2. The communication controller of claim 1 further comprising:

an instruction memory bank, coupled to the first processor, for storing tasks;

a first memory bank, coupled to the first processor, for storing data to be processed by the first processor;

a first direct memory access controller, coupled to the first processor and to the first external bus, for fetching information stored within an external memory bank which is coupled to the first external bus;

a second direct memory access controller, coupled to the first processor and to the second external bus, for fetching information stored within an external memory bank which is coupled to the second external bus; and

a plurality of peripherals, coupled to the scheduler and to the first memory bank, for buffering between the multiple communication channels and the first memory bank.

3. The communication controller of claim 2 wherein the scheduler stores a plurality of stack pointers;

wherein a stack pointer is associated with a task;

wherein the scheduler sends the first processor a selected stack pointer, the selected stack pointer is associated with the selected task;

wherein an execution of a task involves updating the selected stack pointer; and

wherein the first processor sends the scheduler the updated selected stack pointer, when the first processor stops to execute the selected task.

4. The communication controller of claim 3 further comprising:

a peripheral; and

a peripheral bus, coupled to the scheduler and to the peripheral.

5. The communication controller of claim 4 wherein a peripheral has two request channels;

wherein the first request channel handles the transmission of data sent from the communication controller to a communication channel;

wherein the second request channel handles the reception of data sent to the communication controller from a communication channel;

wherein the first request channel sends the scheduler a transmit request when the first request channel can receive data to be sent to the communication channel; and

wherein the second request channel sends the scheduler a receive request when the second request channel received data from a communication channel.

6. The communication controller of claim 5 wherein the scheduler comprising:

a request selector, coupled to the peripherals, for receiving transmit request and receive requests, and selecting a selected request;

a plurality of stack pointer registers, for storing a plurality of stack pointers;

a stack pointer input multiplexer, coupled to the plurality of the stack pointer registers and to the first processor, for writing stack pointers to the plurality of stack pointer registers; and

a stack pointer output multiplexer, coupled to the plurality of the stack pointer registers, to the first processor and to the request selector, for sending the selected stack pointer to the first processor.

7. The communication controller of claim 6 wherein the first direct memory access controller and the second direct memory access controller comprising:

a direct memory access request queue, coupled to the first processor, for storing a plurality of direct memory access requests; and

an enable unit, coupled to the direct memory access request queue and to the scheduler, for masking transmit requests from first request channels associated with the direct memory access requests stored in the direct memory access memory controller, and for masking receive requests from second request channels associated with the direct memory access requests stored in the direct memory access memory controller.

8. The communication controller of claim 7 wherein the first direct memory access controller and the second direct memory access controller further comprising:

a request bypass register, for storing a direct memory access request;

an input multiplexer, for determining whether to store a direct memory access request within the direct memory access request queue or within the request bypass register; and

an output multiplexer, coupled to the first memory bank, to the direct memory access request queue and to the bypass request register, for selecting the direct memory access request stored in the request bypass register, if the request bypass register stores a valid direct memory access request.

9. The communication controller of claim 8 wherein the direct memory access request queue has a plurality of memory words;

wherein each memory word has a first portion and a second portion;

wherein the second portion is for storing direct memory access requests; and

wherein the first portion is for storing a label, the label indicating the request channel which is associated to the direct memory access requests stored within the second portion.

10. The communication controller of claim 7 wherein a transmit request from a first request channel is masked when the enable unit within one of first direct memory access controller and second direct memory access controller masks a transmit request from the first request channel;

and

wherein a receive request from a second request channel is masked when the enable unit within one of first direct memory access controller and second direct memory access controller masks a receive request from the second request channel.

11. The communication controller of claim 10 further having a block transfer machine, for transferring data from the peripherals to the first memory bank and from the first memory bank to the peripherals;

wherein the block transfer machine comprising;

a bit field unit, coupled to the peripherals, for manipulating data;

a CRC machine, coupled to the peripherals, for performing CRC checks;

a BTM data register, coupled to the CRC machine, the data manipulator and the first memory bank, for storing data to be sent from the first memory bank to the peripherals and for storing data to be written to the first memory bank; and

a BTM control unit, coupled to the CRC machine, to the data manipulator and the BTM data register, for controlling the block transfer machine.

12. The communication controller of claim 11 wherein the first memory bank has a plurality of sections, each section is coupled to the first processor, the second processor, the direct memory access controller, the second direct memory access controller and the BTM, wherein each section comprising:

a memory array, for storing information;

a memory selector, for selecting a selected device out of the first processor, the second processor, the direct memory access controller, the second direct memory access controller and the BTM;

a data multiplexer, for enabling the transmission of data between the selected device and the memory array; and

an address multiplexer, for enabling the selected device to send an address word to the memory array.

13. The communication controller of claim 5 wherein the external memory bank has a plurality of buffers, for storing data;

wherein the external memory bank further has buffer descriptors, for storing a pointer, a status and control field and a length field;

wherein the pointer points to a buffer;

wherein the length field defines the length of the buffer that is referenced by the pointer; and

wherein the status and control word has a F/S field, which indicates which one of the first processor and the second processor can access the buffer referenced by the pointer.

14. The communication controller of claim 13 wherein a buffer stores data associated with a request channel;

wherein a set of buffers associated with a single request channel form a circular queue;

wherein the status and control word comprises of a wrap field, for indicating whether the buffer referenced by the buffer descriptor having the wrap field, is the last buffer in the set;

wherein a buffer stores data from a single data frame;

wherein each buffer comprises of a plurality of memory words;

wherein the first memory bank stores a temporary pointer; and

wherein a temporary pointer points to the next memory word to be processed by the first processor.

15. The communication controller of claim 14 wherein the first processor sets the F/S field after the buffer referenced by the buffer descriptor is processed by the first processor;

and

wherein the second processor resets the F/S field after the buffer referenced by the buffer descriptor is processed by the second processor.

16. The communication controller of claim 14 wherein when the first processor performs a task switch it saves the updated temporary pointer in the first memory bank;

and

wherein when the first processor starts to execute instructions out of a task, the first processor fetches the temporary pointer.

17. A method for handling transactions of data streams, the data streams being comprised of frames, wherein a transaction of a frame is handled by the execution of a task, wherein executing a task involves fetching information from an external unit, the method comprises of the following steps:

checking if there is a need to handle a transaction;

executing a task, if there is a need to handle a transaction, until the task ends or until the execution of the task involves fetching information from an external unit;

jumping to step of checking if there is a need to handle a transaction, if the task ended; and

else, initiating a process of fetching the information from the external unit, stopping the execution of the task that involved fetching information from an external unit and jumping to step of checking if there is a need to handle a transaction.

18. The method of claim 17 wherein the execution of a task is stopped when there is a need to receive a portion of a frame from a communication channel.

19. A method for operating a communication controller for receiving, transmitting and processing high speed data streams, the data streams are comprised of frames, the communication controller coupled to a plurality of communication channels and to an external units, the communication controller having a first processor for controlling data stream transactions;

wherein the first processor controls a transaction of a frame by executing a task;

a second processor for handling high level management and communication protocol functions;

a first external bus, coupled to the first processor and the second processor, for coupling the first processor and the second processor to external units;

a second external bus, coupled to the first processor and the second processor, for coupling the first processor and the second processor to external units; and

a scheduler, coupled to first processor, for sensing if there is a need to execute a task, and for selecting which task to execute;

the method comprising of the following steps;

checking if there is a need to handle a transaction;

executing a task, if there is a need to handle a transaction, until the task ends or until the execution of the task involves fetching information from an external unit;

jumping to step of checking if there is a need to handle a transaction, if the task ended; and

else, initiating a process of fetching the information from the external unit, stopping the execution of the task that involved fetching information from an external unit and jumping to step of checking if there is a need to handle a transaction.

20. The method of claim 19 wherein the communication controller further has an instruction memory bank, coupled to the first processor, for storing tasks;

a first memory bank, coupled to the first processor, for storing data to be processed by the first processor;

a first direct memory access controller, coupled to the first processor and to the first external bus, for fetching information stored in an external memory bank coupled to the first external bus;

a second direct memory access controller, coupled to the first processor and to the second external bus, for fetching information stored an external memory bank coupled to the second external bus;

a plurality of peripherals, coupled to the scheduler, and to the first memory bank, for buffering between multiple communication channels and the first memory bank;

wherein each peripheral is comprised of two request channels;

wherein the first request channel handles the transmission of data sent from the communication controller to a communication channel;

wherein the second request channel handles the reception of data sent to the communication controller from a communication channel;

wherein request channel parameters define the status of a request channel;

wherein communication channel parameters define the status of a communication channel;

wherein the external memory bank has a plurality of buffers, for storing data;

wherein the external memory bank further has buffer descriptors, for storing a pointer, a status and control field and a length field;

wherein the pointer points to a buffer;

the method comprising of the following steps;

starting a task;

reading request channel parameters;

fetching communication channel parameters and checking communication channel parameters which indicate whether the task involves processing the first data word in a frame;

if the task involves processing the first data word in a frame performing the following steps;

fetching buffer descriptors;

setting temporary pointer to the value of pointer within buffer descriptor;

checking whether the buffer descriptor is enabled, wherein if the buffer descriptor is not enabled, waiting until buffer descriptor is enabled;

fetching the temporary pointer;

else, jumping to step of fetching the temporary pointer;

moving data from a communication channel to an external unit, if receiving data and moving data from an external unit to a communication channel, if transmitting data;

checking if a data frame ended and if a buffer ended;

updating communication channel parameters and jumping to step of fetching buffer descriptor, if a buffer ended;

sending an end of frame indication, closing a buffer descriptor, updating communication channel parameters and jumping to step of starting a task, if a frame ended; and

else, updating temporary pointer and jumping to step of moving data.